1997
DOI: 10.1109/16.595934
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A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs

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Cited by 46 publications
(13 citation statements)
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“…In order to balance the lower volatility of (2), increasing of the reservoir temperature to 80 uC and reduction of the system pressure to 1 Torr were employed to assist the vaporization and transport of the precursor. It was observed that the successful deposition of an Ru thin film was realized at all three temperature settings (275, 325 and 375 uC), which were slightly lower than those used for the hfac complex (1). Concurrently, the electrical resistivity of the thin films deposited at temperatures below 325 uC was found to be significantly greater than samples obtained at 375 uC.…”
mentioning
confidence: 83%
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“…In order to balance the lower volatility of (2), increasing of the reservoir temperature to 80 uC and reduction of the system pressure to 1 Torr were employed to assist the vaporization and transport of the precursor. It was observed that the successful deposition of an Ru thin film was realized at all three temperature settings (275, 325 and 375 uC), which were slightly lower than those used for the hfac complex (1). Concurrently, the electrical resistivity of the thin films deposited at temperatures below 325 uC was found to be significantly greater than samples obtained at 375 uC.…”
mentioning
confidence: 83%
“…13 For deposition of Ru metal, the sample reservoir was maintained at 28 uC and 50 uC for complex (1), and 80 uC for complex (2); while RuO 2 thin films were deposited using pure O 2 carrier gas. The flow rate of the carrier gas was adjusted to 10-20 sccm, the sample reservoir was loaded with y50 mg of CVD source reagent, and the deposition time was set to a period of 20-40 min.…”
Section: Cvd Proceduresmentioning
confidence: 99%
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“…The same bilayer structure has already been proposed and investigated within a RuO2/Ru/TiN/TiSix/poly-Si storage node. 86 Oxygen transport studies have also been reported for Pt and Re protective layers, considered also as bottom gate electrodes for MOS-like devices. 87,88,89 In the case of gate dielectric layers for CMOS and memory (DRAM) devices, several (usually high-K) binary oxides such as Ta2O5, 90,91 Y2O3, 92,93 Al2O3, 91,94,95,96 HfO2, 97,98,99,100 ZrO2, 34,101,102,103 and TiO2, 104,105,106 and also perovskite materials such as SrTiO3 and (Ba,Sr)TiO3 have been investigated, 107,108 according to their electrical and/or other physical properties after/or during growth.…”
Section: Current Status 1231 Microelectronic (Dram and Cmos) Devicesmentioning
confidence: 99%