A Stagger-Tuned Transimpedance Amplifier

Abstract

A new transimpedance amplifier (TIA) design procedure using stagger tuning with inverted transformer coils is described in this paper. A broadband TIA, realized using the proposed staggered design technique that enhances the transimpedance limit and the bandwidth while only adding small passband gain ripple, was implemented in a 0.13-μm standard CMOS process. The TIA achieves a 3-dB bandwidth of 33 GHz with a 150 fF photodiode capacitance. The TIA transimpedance gain is 43.8 dB with ±8 ps group-delay variation over the entire bandwidth. The circuit occupies an active area of 250 μm × 260 μm and consumes 9 mW from a 2 V supply. Despite operating with much larger photodiode capacitance, the TIA achieves the highest figure of merit, and occupies smaller area while consuming the least amount of power among previously published TIAs designed for the same data rate in similar technologies.

A low‐power CMOS transimpedance amplifier in 90‐nm technology for 5‐Gbps optical communication applications

“…In the recent years, researchers have discussed and analyzed different circuit structures and techniques to improve the performance of the TIA circuits for using in high‐speed communication applications. These techniques are as follows: f T doubler, shunt peaking, inductive peaking and series peaking technique, active feedback, 3D inductor serial peaking, slew boosting, Regulated Cascode (RGC), common‐drain feedback, T‐coil inductor matching, negative impedance compensation, double three‐order active feedback, stagger tuning, Л‐network, voltage‐current feedback, the zero and pole cancellation, and a three‐dimensional inductor converter . In addition, structures that are usually used as TIA building blocks to alleviate the bandwidth reduction are as follows: RGC structure, stagger tuning, and T‐coil inductor matching.…”