A static scheduling scheme of multicore compiler for loop load imbalance in OpenMP

Chen, Benbin; Guo, Donghui

doi:10.1109/icasid.2014.7064954

Cited by 5 publications

(5 citation statements)

References 7 publications

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“…However, the tests cover almost all of the functions in GCC directory. And more (6) and (7), we can caculate the K p and load(IR p ) for each processor showed in Table 7 compared the new static scheduling and default static scheduling schemes [3] in OpenMP. From the Table 7, we know that the chunk size K p is the same with 25 for each processor, but the load is very different in the default static scheme.…”

Section: Case 3: Comparative Analysis Of Compiler and The Codes Covermentioning

confidence: 99%

“…In this way, assume that the loop body is the actually executed statements which are contents of the loop variable I [3]. If iteration variable of loop is I, assume that IR is the loop task set with iteration variable I, and then IR p is the subset of loop task for each processor [3], we have:…”

Section: Description Of New Static Allocationmentioning

confidence: 99%

“…Parallel speedup is the ratio of serial and parallel program execution time of the program execution time. Formula follow is the speedup of shared memory parallel processors assuming each processor usually has the same processing capacity [3].…”

Section: Openmp and Allocation And Scheduling For Loop Parallelmentioning

confidence: 99%

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A high quality compiler tool for application-specific instruction-set processors with library and parallel supports

Chen

King

et al. 2015

Multimed Tools Appl

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Developing a high quality compiler tool for application-specific instruction-set processors (ASIPs) including DSP for multimedia application is challenging. The specialization in ASIPs often calls for extensions at the high-level languages to allow the designers to exploit the specialized capabilities. This in turn requires the frontend of the compiler to handle the new syntax and carry the intentions of the designers across to the compiler backend implementations. The backend implementations also require extra efforts for optimized uses of the specialize features of ASIPs. Meanwhile, because of the diversity of the application, it is necessary to make full use of the compiler to complete supports and to make up some shortages of ASIP processors, the corresponding library functions are increased to support of certain operations, such as floating point arithmetic that may not be supported in ASIPs. With the development of the embedded parallelism, the advanced ASIP compilers need the support of parallelism for future application. This paper describes the High-performance C Compiler (HCC) and its specific implementation for an industrial ASIP and its family processors. HCC is a C language compiler extended and retargeted from GCC. A compiler extension framework is proposed processing programming syntax extensions of standard ANSI C for the ASIPs. With target-specific implementation, the adding optimized arithmetic functions library and chips definition file (CDF) as well as the header files for corresponding ASIPs, HCC compiler could be enhanced for the processing capabilities of target processors. Finally, this paper describes a new compiler static allocation and scheduling scheme for loop Multimed Tools Appl parallelization based on the OpenMP specification to improve the load imbalance. We have conducted analysis and extensive experiments to verify the correctness and effectiveness of the HCC compiler with the presented ideas. The results show that HCC compiler has a stable performance with excellent codes quality and it has been used in market.

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Section: Case 3: Comparative Analysis Of Compiler and The Codes Covermentioning

confidence: 99%

Section: Description Of New Static Allocationmentioning

confidence: 99%

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A high quality compiler tool for application-specific instruction-set processors with library and parallel supports

Chen

King

et al. 2015

Multimed Tools Appl

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“…Diversas estratégias para realizar o escalonamento de laços foram propostas para satisfazer as mais variadas restrições [Hajieskandar and Lotfi 2010, Olivier et al 2012, Ding et al 2013, Chen and Guo 2014. No entanto, selecionar estratégias de escalonamento mais adequadas para aplicações específicas aindaé um desafio.…”

Section: Trabalhos Relacionadosunclassified

Uma Metodologia Baseada em Simulação e Algoritmo Genético para Exploração de Estratégias de Escalonamento de Laços

Penna

Castro

Freitas

et al. 2015

Anais Do XVI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2015)

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Na Computação de Alto Desempenho, a carga de trabalho de aplicações paralelas deve ser balanceada entre as threads para obtenção de um melhor desempenho. Nesse trabalho é proposta uma metodologia que possibilita o projeto e a exploração de novas políticas de escalonamento de laços. Essa metodologia emprega a técnica de simulação para estudar as principais estratégias existentes e um algoritmo genético para explorar o espaço de soluções do problema. A metodologia proposta auxiliou no projeto de uma nova estratégia de escalonamento de laços que se mostrou ser até 32.3x melhor em ternos de balanceamento de carga que as políticas existentes.

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“…Chen and Guo' solution. Recently, Chen and Guo [42] proposed an enhancement of the static scheduling of OpenMP (based on FSC) which changed static chunk sizes in order to better exploit load balance of loops. Thus, they adapted FSC to a dynamic approach.…”

Section: Dynamic Schedulingmentioning

confidence: 99%

Design and evaluation of a Thread-Level Speculation runtime library

López¹

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It is very likely that, in the next years, shared-memory systems with hundreds or even thousands of computational units will become commonplace. Since parallel programming is conceptually difficult, and to take advantage of these platforms, it is desirable to have compiling and/or runtime systems that automatically extract all the available parallelism of a sequential application. Although many parallel processing approaches have been developed in the last decades, most automatic parallelization proposals are focused on codes with no hurdles. Speculative parallelization (SP) techniques arise as a more general solution, allowing the parallel execution of any code, even in the presence of dependence violations. To ensure that, SP approaches rely on a runtime monitor responsible for ensuring that the results of the parallel execution match the expected output of the original, sequential code. This technique, based on the optimistic assumption that no dependences will arise when executing the code in parallel, launches threads that execute different fragments of the sequential code at the same time. If a dependence violation is detected, the offending threads are stopped and restarted with the correct values, thus ensuring that the execution follows sequential semantics. Our contribution in this field includes (1) a new, easy-to-use speculative runtime library; (2) new proposals which allow to decrease the number of memory accesses involved in speculative operations, as well as some advice to decrement the memory footprint; (3) research on new scheduling methods focused on the dynamic management of chunks of iterations in speculative executions; (4) an hybrid approach which implements speculative parallelism using transactional memory to handle its critical sections; and (5) an analysis of the speculative techniques in one of the most state-of-the-art devices as are Intel Xeon Phi coprocessors. Speculative parallelization is a lively research field. Our results show that these techniques have the potential of leading to considerable improvements in the performance of many applications. We expect that this work, among others, will foster the use of SP-based solutions in commercial compilers and shared-memory parallel programming models.

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A static scheduling scheme of multicore compiler for loop load imbalance in OpenMP

Cited by 5 publications

References 7 publications

A high quality compiler tool for application-specific instruction-set processors with library and parallel supports

A high quality compiler tool for application-specific instruction-set processors with library and parallel supports

Uma Metodologia Baseada em Simulação e Algoritmo Genético para Exploração de Estratégias de Escalonamento de Laços

Design and evaluation of a Thread-Level Speculation runtime library

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