A static verification approach for architectural integration of mixed-signal integrated circuits

Mukhopadhyay, Rajdeep; Komuravelli, Anvesh; Dasgupta, Pallab; Panda, Satyajit; Mukhopadhyay, Siddhartha

doi:10.1016/j.vlsi.2009.05.002

Cited by 1 publication

(1 citation statement)

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“…For the verification of mixed-signal circuits, the behavioral description of the mixed-signal circuit was transformed into a discrete model [18], and the verification was performed by formal digital verification technique. The static verification method was proposed [19], the method can verify the proper integration for the analog and mixed-signal macro-blocks into an integrated circuit, and the validity of the interconnections between the blocks was verified. The modeling and verification approach of analog/RF circuits in the presence of noise and process variations were presented [20], the approach made use of stochastic differential equations.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

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Section: Introductionmentioning

confidence: 99%