A statistical approach for design and testing of analog circuitry in low-cost SoCs

Abstract

A novel design-for-testability approach is proposed, which is derived from the aggressive probabilistic targets set forth for the yield and quality to be achieved in the massproduction of high-volume low-cost transceiver SoCs, thus requiring solutions that are fundamentally different from the traditional approaches. Statistical analysis is presented as the basis for the proposed approach, and specific guidelines are defined and demonstrated through examples. The proposed approach, based on built-in-self-testing (BIST) of RF/mixedsignal functions in the transceiver SoC, relies on digital processing resources that are typically available within the SoC at no additional cost and may aid in its testing and calibration. The important roles of characterization and built-in-selfcalibration and compensation in this context are also defined.

Built-In Measurements in Low-Cost Digital-RF Transceivers

“…Statistical analyses, demonstrating the validity of the crude-measurement approach for final-testing, are provided in [17] and summarized in the following subsections.…”

“…However, with such approach, the test program is still forced to measure that performance parameter accurately, resulting in the need for accurate analog ATE, as well as the need to fail devices that do not meet the criteria, both of which impact profitability. Contrarily, the approach described in [17] proposes the use of 'soft specifications', wherein the statistical distribution of a performance parameter, characterized over sufficiently large volumes, is communicated to customers. For example, a receiver's sensitivity may be within a certain range around the typical value with some 99% probability, and up to 2 dB inferior to that value with less than 1% probability.…”

“…A post-fabrication approach to dealing with such scenario would be the redefinition of the performance specifications, which are anyway usually somewhat arbitrary numerical limits that presumably correspond to user experiences, as stated in [17]. As explained in Sect.…”

Mismatch reduction technique for transistors with minimum channel length

“…Moreover, rising variability from technology scaling has been identified as one of the main CMOS fabrication challenges due to its influence on the functionality, yield, and profitability of products [4]. Therefore, besides designing to meet specifications, it becomes increasingly important to decrease the statistical variations of circuit performance parameters in order to improve production yields and to reduce the manufacturing test cost by employing new statistical design approaches such as those described in [7]. A design technique towards this goal is presented in this letter.…”