A Step Toward Real-Time Time–Frequency Analyses with Varying Time–Frequency Resolutions: Hardware Implementation of an Adaptive S-transform

Radovic, Nevena; Ivanovic, Veselin N.; Djurović, Igor; Simeunović, Marko; Sejdić, Ervin

doi:10.1007/s00034-022-02203-3

Cited by 5 publications

References 37 publications

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A Compact Implementation of Shadow on an IoT Processor

Chen,

Liu,

Guo

et al. 2024

Circuit Theory & Apps

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Shadow is a lightweight AND‐RX block cipher adapted for resource‐constrained devices. In this paper, software and hardware optimizations are proposed respectively for Shadow to enhance its implementation performance. For software optimization, this paper first proposes a data pre‐processing scheme based on the structural characteristics of the round function. It further improves the optimization effect of the barrel shifter instruction while simplifying the implementation process of the round function. Note that the optimization strategy is also applicable to other AND‐RX ciphers. Secondly, this paper proposes a new NX operation implementation scheme that can effectively reduce its instruction cycles. In round‐based architecture, experimental results show that our scheme effectively reduces code size by 24.7%, Flash consumption by 12.6%, and total instruction cycles by 25.1%. Meanwhile, in the fully unrolled architecture, our scheme reduces code size by 30.8%, Flash consumption by 29.8%, and total instruction cycles by 28.1%. For hardware optimization, this paper proposes a low‐resource implementation scheme by constructing a generic formula for NX operation. In ASIC implementation, our scheme reduces hardware resources by 72.3%. In FPGA implementation, the number of LUTs and Slices is reduced by 30% and 28.6%, respectively. Overall, the proposed optimization scheme for Shadow has better performance in hardware and software implementation.

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