A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation

Davis, Jeffrey A.; De, Vivek; Meindl, J.D.

doi:10.1109/16.661219

Cited by 252 publications

(249 citation statements)

References 8 publications

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“…The uses of Rent's rule within a chip find that the frequency of wires of a given length decreases with increasing length approximately as a power −0.6 ± 0.2 of the wire length with a rather abrupt termination at a maximum length. They are successful in being able to fit the length distributions of manufactured working chips (Donath 1979, Davis et al 1996, 1998a). …”

Section: Wire Lengthsmentioning

confidence: 99%

“…The point is that as devices are made smaller and their density on a chip increases, adding more layers of wire accommodates the required increase in wire density without too much sacrifice of wire width. This argument is an oversimplification in that the different layers may have different widths w j , but wire area is the dominant determinant of chip area today (Davis and Meindl 1998, Davis et al 1996, 1998a, 1998b. The length of wire per unit area, D w , is a useful characterization of the wire density.…”

Section: Space For Wiresmentioning

confidence: 99%

“…A number of authors have assumed that Rent's rule is also applicable to connections to any arbitrary portion of a chip and used it to derive wire length distributions on a chip (Donath 1979, Davis et al 1998a, 1998b. While this application is not unreasonable and may be correct (Christie and Stroobandt 2000), it hardly follows from the rather different original significance of Rent's rule, which was an experimental result in cases where the limited availability of connections between package levels and the delays and distortion of signals in the connectors provided a strong incentive for system designers to minimize the number of transitions to another level of the package.…”

Section: Wire Lengthsmentioning

confidence: 99%

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Physical limits of silicon transistors and circuits

2005

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A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented.

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Section: Wire Lengthsmentioning

confidence: 99%

Section: Space For Wiresmentioning

confidence: 99%

Section: Wire Lengthsmentioning

confidence: 99%

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Physical limits of silicon transistors and circuits

2005

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“…If the designer now owns twice as many of these 50K gate blocks, then either she has to manually intervene for twice as many wires, or the CAD flow must now be able to handle wires longer than L crit . The cumulative wire distribution function from Davis [13] gives the longest wire (in gate pitches) as the percentage of wires varies, as shown below. Here, area utilization is assumed to be 60%.…”

Section: Cad Implicationsmentioning

confidence: 99%

Interconnect Scaling Implications for CAD

Ho¹,

Mai²,

Kapadia³

et al. 1999

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Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention. IntroductionWith process technologies capable of fabricating a billion transistor chip on the horizon, the CAD community faces many new challenges. Notably, interconnect scaling in deep submicron processes may force a fundamental change in current ASIC design methodologies. If interconnect delay becomes a significant fraction of total delay, timing convergence for standard-cell design blocks will become difficult or impossible to achieve with current, crude, fanout-based wire load models. Designers will need new tools and methods to synthesize large blocks in deep submicron technologies.In a 1998 ICCAD tutorial, Sylvester and Keutzer carried out a detailed analysis of interconnect scaling and its potential effects on CAD methodologies [1] [2]. By examining the scaling of average length wires, they concluded that CAD tools are adequate for future module-level designs. We examine the sensitivity of their analysis to a range of possible technology scaling assumptions by modeling their simulations with an RC tree delay model.Since design speeds and timing convergence in synthesis flows are typically constrained by long wires, not averagelength ones, we extend the analysis to long wires. We show that for a fixed complexity design, the number of long wires grows slowly with scaling. If chip complexity remained constant, this increase in long wires could be handled by small improvements in today's CAD design flow. Unfortunately exponentially increasing die capacity exacerbates the increasing number of long wires per module by driving up the number of modules. Thus, with constant design team size, the number of gates per designer will grow exponentially. To prevent the per-designer workload from also growing exponentially the percentage of wires that need manual intervention must fall exponentially. This implies that future tools must handle a greater per...

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“…Choosing a power-law SW network may be preferable, as it lowers the cost associated with communications. It was also recently argued [7] that "wiring-cost" considerations for spatially embedded networks, such as cortical networks [9] or on-chip logic networks [10], can generate such power-law-suppressed link-length distribution. A physical example of such a power-law SW network arises in diffusion on a randomly folded polymer discussed below [11,12].…”

mentioning

confidence: 99%

Diffusion Processes on Power-Law Small-World Networks

2005

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We consider diffusion processes on power-law small-world networks in different dimensions. In one dimension, we find a rich phase diagram, with different transient and recurrent phases, including a critical line with continuously varying exponents. The results were obtained using self-consistent perturbation theory and can also be understood in terms of a scaling theory, which provides a general framework for understanding processes on small-world networks with different distributions of long-range links.PACS numbers: 89.75. Hc, 68.35.Ct, 05.40.Fb, 89.20.Ff Studying diffusion-related processes on networks, one can gain insight into synchronization [1] and spreading phenomena in natural, artificial, and social systems [2]. In this Letter, we consider a class of models on smallworld (SW) networks [3] with a power-law probability distribution of long-range links, where the probability of two nodes being connected goes as r −α , with some exponent α [4,5,6,7]. Such a structure can emerge in synchronization problems of distributed computing [8] where synchronization is achieved by introducing random communications between distant processors. Choosing a power-law SW network may be preferable, as it lowers the cost associated with communications. It was also recently argued [7] that "wiring-cost" considerations for spatially embedded networks, such as cortical networks [9] or on-chip logic networks [10], can generate such power-law-suppressed link-length distribution. A physical example of such a power-law SW network arises in diffusion on a randomly folded polymer discussed below [11,12].The addition of random long-range links to a regular d-dimensional network, producing a SW network, leads in many cases to a crossover to mean-field-like behavior [13], effectively becoming equivalent to averaging over the long-range links in an annealed fashion. Here we focus on systems where it is not the case, and the contrast between the quenched and annealed systems is strong [5,14]. We develop a perturbative method for the quenched network, which is asymptotically exact, as confirmed by numerics.Varying the exponent α, controlling the distribution of length of the links, the diffusive dynamics gives rise to a rich phase diagram, as the connection topology interpolates between the original "plain" SW (α=0) and the purely short-range connected (α=∞) network. The phase diagram can also be understood in terms of simple scaling ideas, showing that the breakdown of mean-field theory is associated with the relevance of the operator for scattering off a single link.Diffusion-Related Processes-We start with a ddimensional lattice of linear size L and add long-range links, connecting two sites with a probability proportional to pr −α , where r is the distance between the two sites, p is the probability of a site to have a random link, and α is the exponent of the decay, ranging from 0 to ∞. Although the original problem can have only one random link between two distant sites, the analytics are slightly simpler if pairs of sites may be ...

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A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation

Cited by 252 publications

References 8 publications

Physical limits of silicon transistors and circuits

Physical limits of silicon transistors and circuits

Interconnect Scaling Implications for CAD

Diffusion Processes on Power-Law Small-World Networks

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