HDL model validation can involvc billions of cyclcs of simulations. To improvc validation efficiency wc propose a stopping rule to detcnninc whcn ,\ validation phase using a spccific type of patterns has reachcd a point of diminishing return.
Keywords:Bchavioral Model Vcrification, Statistical Stopping Rulcs, VHDL.
INTRODUCTIONWith rapid advances in VLSI technology. the complexity of VLSI chips has reached millions of gates per chip. Modeling of these complex chips often resulted in complex behavioral models with thousands of lines of HDL (Hardware Description Language) code. Verification of HDL models has, therefore, become a critical and a time consuming task. The conventional approach to verifying HDL models is through extensive functional simulations. Design engineers who wrote the HDL models are often responsible for generating test cases to verify the models. This approach works reasonably weil for small to medium size HDL models. For large and complex HDL models, this approach is less effective because of the exponentially increasing input space that has to be explored during verification. Large and complex designs that employed the conventional approach often resulted in a huge amount oftest patterns applied to the models. For example, in verifying the PowerPC-601 chip's behavioral