A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits

Sanyal, Subrata; Patra, Amit; Dasgupta, Pallab; Bhattacharya, Mukul

doi:10.1109/ats47505.2019.00025

Cited by 9 publications

(1 citation statement)

References 20 publications

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“…In addition to these expectations from the industry, the requirements from standards such as ISO26262 Standard for functional safety [3] recommends an automotive integrated circuit (IC) to have a very high defect coverage (usually greater than 90%) put additional emphasis on time-efficient defect screening techniques [4], [5]. Furthermore, as discussed, the circuits are becoming progressively more complex and integrated, the number of defects to be tested are also increasing proportionately which in turn increases the defect-simulation time.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Saikiran

Sekyere

Ganji

et al. 2022

Preprint

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Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods. Furthermore, the overall development time of integrated circuit can be reduced by reducing the defect simulation time. In this work, we present a simple and time-efficient defect simulation framework for pre-silicon testing of AMS circuits. In our method, a given defect model is realized using Verilog-A modules and tests multiple defects in a circuit in a single-run simulation. In contrast to the conventional defect simulation framework, our method saves simulation time by avoiding the repetitive work of generating a netlist for each defect and by reducing the time overhead for the simulator to interface with data/file-handling system. To strongly validate our proposed framework, we use diverse AMS circuits such as operational amplifier (op amp), fast transient flipped-voltage follower based low-dropout regulator (FVF LDO) and Successive-approximation-register (SAR) analog-to-digital converters (ADC). For DC testing schemes used for op amp and LDO testing, we show that our proposed framework reduces the simulation time to less than one-tenth (1/10th) in comparison with conventional framework. On the other hand, for the transient testing scheme, the proposed framework reduces the simulation time to less than 50% of the conventional framework. Furthermore, we also show that there is no negative impact on the defect coverage using the proposed framework.

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Section: Introductionmentioning

confidence: 99%