A Structured ASIC Design Approach Using Pass Transistor Logic

Gulati, Kanupriya; Jayakumar, Nikhil; Khatri, Sunil P.

doi:10.1109/iscas.2007.378019

Cited by 10 publications

(14 citation statements)

References 8 publications

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“…The experimental results demonstrate that on average, our approach has a delay penalty of 40%, an area penalty of 12%, and a power increase of 7% compared to an ASIC design approach. This is better than the previously reported structured ASIC approach of [8] which has a delay overhead of 101% and an area overhead of 508% compared to the ASIC approach. We also performed lithographical simulations of the poly and metal masks of the designs implemented using our approach as well as ASIC design approach.…”

Section: Introductionmentioning

confidence: 66%

“…The delay and area overhead of this approach were on average 101% and 508% respectively. In contrast to [14] and [8] the approach of this paper has a significantly lower overhead 40% for delay, and 12% for area compared to ASIC approach.…”

Section: Previous Workmentioning

confidence: 91%

“…Other recent structured ASIC approaches include [14] and [8]. In [14] the authors use a fixed size Programmable Logic Array (PLA) as the underlying structure to implement logic.…”

Section: Previous Workmentioning

confidence: 99%

“…The average delay and area overhead of this approach were 189% and 396%. Similarly, in [8], the authors utilize a Pass Transistor Logic (PTL) based circuit fabric to implement the design. The delay and area overhead of this approach were on average 101% and 508% respectively.…”

Section: Previous Workmentioning

confidence: 99%

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A lithography-friendly structured ASIC design approach

Gopalani

Garg

Khatri

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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Integrated circuit manufacturing costs are increasing with decreasing device feature sizes, due to significant increases in mask costs. At the same time, systematic processing variations due to optical proximity effects are also increasing, making it harder to predict the circuit behavior with fidelity. Therefore, there is a need to implement designs using regular circuit structures. In this paper, we present a new structured ASIC approach which utilizes an array of 2-input NAND gates. Our NAND2 array based circuit implementation reduces manufacturing costs, and design turn-around times because different designs can share the same masks up to the poly layer. The regular layout structure of our NAND2 array also helps in reducing systematic variations. We compared the performance of our NAND2 array with the ASIC approach by implementing several benchmark circuits using both methods. The experimental results demonstrate that on average, our approach has a delay penalty of 40%, an area penalty of 12%, and a power increase of 7%, compared to an ASIC design approach. This is better than the previously reported structured ASIC approaches. We also performed lithographical simulations of the poly and metal masks of the designs implemented using our approach as well as the ASIC design approach. These lithographical simulation results demonstrate that our approach has lower errors on the poly and the Metal1 layers by 7% and 24% respectively, compared to the ASIC approach.

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Section: Introductionmentioning

confidence: 66%

Section: Previous Workmentioning

confidence: 91%

“…Other recent structured ASIC approaches include [14] and [8]. In [14] the authors use a fixed size Programmable Logic Array (PLA) as the underlying structure to implement logic.…”

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

See 2 more Smart Citations

A lithography-friendly structured ASIC design approach

Gopalani

Garg

Khatri

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

Self Cite

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“…The group led by Fujino [28] proposed VPEX2 architecture based on via-configurable Exclusive OR and inverter. The group led by Khatri proposed via-configurable NAND2 [35], PLA [39], and ITE-cell [40]. Some VCLBs are designed specifically for improving manufacturing yield [35], [41], [42].…”

Section: A Related Workmentioning

confidence: 99%

Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

Tung

Lin

et al. 2012

IEEE Trans. VLSI Syst.

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A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic gate. We devise four new VCLBs and construct several cell libraries based on these VCLBs. We develop a design flow mostly using industrial design tools and propose a method to evaluate VCLB viability. The experimental results show that a medium-grained VCLB that realizes a rich set of logic functions attains the best performance.Index Terms-Regular fabric, standard cell, structured application-specific integrated circuits (ASICs), via-configurable logic block.

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