A study comparing current and voltage combining techniques for CMOS power amplifiers for WLAN applications

Abstract

This article presents CMOS power amplifiers for WLAN applications. These power amplifiers use current and voltage combining techniques for simultaneous improvement of the output power and efficiency, respectively, and are analyzed to determine which technique is more suitable for WLAN applications. The power amplifiers are fabricated with a 180 nm CMOS process. Their performance is verified using an 802.11 g modulated signal with 64 QAM, 20 MHz of bandwidth, and 54‐Mbps at 2.7 GHz. The measurements of the current and voltage combining power amplifiers show about 21.9 and 21.8 dBm of average output power, respectively, at −25 dB error vector magnitude (EVM), and about 20.2 and 18 dBm of average output power, respectively, at −30 dB EVM for a commercial specification. In addition, the current combining PA is operated in a multi‐mode manner, which saves the power stage current about 225 mA of the power stage current at low power mode. No pre‐distortion technique is required and all components are integrated on the chip.