A study for optimum productivity yield in 0.16&amp;#x00B5;m mixed of wafer fabrication facility

Chik, Mohd Azizi; Yung, Ve Chun; Balakrishna, Puvaneswaran; Hashim, U.; Ahmad, Ibrahim; Mohamad, Bashir

doi:10.1109/smelec.2010.5549356

Cited by 2 publications

(1 citation statement)

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“…Process to fabricate a chip on a wafer required 300 to 1000 steps process re-entrance to similar equipment more than 30% of the total steps, cycle time can be up to 90 days depends to complexity and priority given for a product with minimum of 60 equipment. Notice the ratio between number of steps and equipment is almost 5 times, which is due to the wafer fabrication process is not like a single line assembly process in normal factory instead of re-entrance back to the same process [2] [3]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Discrete event simulation modeling for semiconductor fabrication operation

Chik¹,

Rahim²,

Rejab³

et al. 2014

2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)

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This research is to investigate simulation modeling method for semiconductor fabrication factories (FAB) that known for complex manufacturing operation from various the literatures. This paper covers literatures from various publications since past 10 years. The significant simulation model used in common and semiconductor fabrication will be selected for evaluation in semiconductor fabrication manufacturing operation scenario with high mixed. Depends to the products mixed configuration, cycle time to complete semiconductor fabrication will take 60 to 90 days. The longer period needed due to wafer process required 300 to 1000 steps, process re-entrance to similar equipment more than 30% of the total steps further increase the complexity with many configuration due to setup changes. The simulation also needs to configure for process queue time, process dedication, several of difference for equipment configuration, capability and capacity. Primary simulation techniques reviewed in this analysis are discrete event, petri-net, gaming, virtual, intelligent, monte carlo and hybrid to understand individual strength and common usage in the market. This research summarized the highest usage, most uses and compatibility in similar operation for semiconductor fabrication. In summary, the research concluded DES is the most suitable technique for simulating FAB operation because of its nature of queuing and leaving concept that fits and resulted to 95% accuracy for WIP forecasting.

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Section: Introductionmentioning

confidence: 99%