A study of failure mechanisms in CMOS & BJT ICs and their effect on device reliability

Abstract

The reliability of electronic systems, used in nuclear power plants, is traditionally estimated with empirical databases such as MIL HDBK-217, PRISM etc. These methods assign a constant failure rate to electronic devices, during their useful life. Currently, electronic reliability prediction is moving towards applying the Physics of Failure approach which considers information on process, technology, fabrication techniques, materials used, etc. The constant failure rate assumption stems from treating failures as random events. Electronics division of BARC is engaged in design & fabrication of CMOS and BJT ICs for nuclear pulse processing and signal conditioning. New microelectronic devices often exhibit infant mortality and wear-out phenomena while in operation. It points to competing degradation mechanisms-electro migration, hot carrier injection, dielectric breakdown etc.-that make a device's useful life different from that predicted by empirical methods.Understanding the dominant mechanisms that lead to device failure -Physics of Failure--is a more realistic approach to reliability prediction. This paper describes common failure mechanisms-encountered in CMOS and BJT ICs and the efforts being taken to quantify these effects in an optical-isolator IC -4N36-which forms a part of the trip generation circuit in neutron flux monitoring systems.

Lifetime estimation for optocouplers using accelerated degradation test

“…Studies on the reliability of optocouplers have been conducted on failure mechanisms, 14,15 analysis of factors affecting the reliability of optocouplers, 16 and reliability prediction without ADT, [17][18][19] Studies of lifetime estimation with ADTs have not been conducted sufficiently except for the following studies. Zhang et al 20 conducted an ADT on optocouplers, where 10 samples were heated in a four-step stress process to four levels of temperatures.…”

Full Custom VLSI Design of On-Line Stability Checkers

“…Q2 Bus2 [3] E2 Bus2 [4] Q3 Bus2 [5] E3 Bus2 [6] Q4 Bus2 [7] E4 Both the Clock and Data lines were tested and signal propagation delay through the chip was estimated on the logic analyzer. …”

“…These defects manifest themselves in phenomena like electromigration [3,4] and hot electron/hole injection [5,6]. These imperfections lead to reliability failures during operation [7].…”