A Study of FinFET Device Optimization and PPA Analysis at 5 nm Node

Luo, Xin; Ding, Yu; Shang, Enming; Sun, Jie; Hu, Shaojian; Chen, Shoumian; Zhao, Yuhang

doi:10.1109/cstic49141.2020.9282502

Cited by 1 publication

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Aggressive technological growth creates large fluctuations in process parameters, resulting in yield, reliability, and testing issues. For every ten degrees of temperature increase, the failure rate of a VLSI chip is stated to double [1][2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Kumar

Kumar²,

Vijayalakshmi³

et al. 2023

Journal of Nanomaterials

View full text Add to dashboard Cite

Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

show abstract