A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel

Hsu, Li Chung; Kadomoto, Junichiro; Hasegawa, So; Kosuge, Atsutake; Take, Yasuhiro; Kuroda, Tadahiro

doi:10.1587/transfun.e98.a.2584

Cited by 5 publications

(2 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The transmitters are enabled right before they are about to be used. In this work, the chip thickness and coil diameter are set to 8 μm and 20 μm, respectively, where the diameter of TCI coils is recommended to be set to 2.5 times as large as the communication distance [11][12][13]. To evaluate crosstalk, the pitch of the coils is regarded as a parametric parameter P, which affects both crosstalk and area efficiency.…”

Section: Baseline Analysismentioning

confidence: 99%

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface

Shiba

Kosuge

Hamada

et al. 2023

IEICE Trans. Electron.

Self Cite

View full text Add to dashboard Cite

This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

show abstract

Section: Baseline Analysismentioning

confidence: 99%

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface

Shiba

Kosuge

Hamada

et al. 2023

IEICE Trans. Electron.

Self Cite

View full text Add to dashboard Cite

show abstract

“…In new computing technologies, some are trying to eliminate such bottlenecks, but they remain a fundamental problem. Since the processing capacity has reached its limit with conventional electrical connection, not only shortening the wiring distance by 3D, but also R&D such as inter-chip near field coupling technology 27) and optical wiring technology 28) as new coupling and wiring technology is required. 2.2.3.…”

Section: Packaging Technologiesmentioning

confidence: 99%

Proposal of disruptive computing (A computing-domain-oriented approach)

Baba

Shimada

Kawamura

et al. 2020

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

The advanced data processing on the edge devices is getting much attention in addition to the performance of cloud computing for big data analysis and artificial intelligence for the advanced cyber-physical systems and Internet of Things. This paper shows the challenges of research and development on disruptive computing which enhance the conventional computing system with high performance and low power consumption. Future R&D challenges in computing technologies involve all technology layers including algorithms, packaging, software, architecture, circuits, devices, and materials. It is important from the perspective of social implementation and efficiency to select technologies suitable for important applications from each technology layer specific to the computing domain and with consideration for the timeline, and to develop technologies through a vertical integration approach. The promoting method of implementing such R&D is also described.

show abstract

A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Shiba

Okada²,

Kosuge³

et al. 2023

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel

Cited by 5 publications

References 12 publications

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface

Proposal of disruptive computing (A computing-domain-oriented approach)

A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Contact Info

Product

Resources

About

A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel

Cited by 5 publications

References 12 publications

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface

Proposal of disruptive computing (A computing-domain-oriented approach)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Contact Info

Product

Resources

About

A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver