A study of the number of tracks required for the reconfiguration of mesh‐connected processor‐element networks

Abstract

The reconfiguration technique for a processor network is among the fault-toleraut techniques in monolithic realization of a multiprocessor network. The problem is composed of the mapping of logical processor element (PE) to physical PE and the physical realization of the logical connections. This paper considers twodimensional mesh array architecture and discusses the roiiting mechanism (required number of tracks) to support the processor mapping b a d on the compensation path. The eight adjacent neighbor is considered in the processor substitution in composing the path. It is shown that four tracks for each channel between PE are sufficient under the condition of no portexchange and no crossover. It is also shown that, when a compensation path exists under the four adjacent neighbor substitution condition, there exists a routing mapping using at most three tracks per channel. As to the evaluation of the number of tracks, the channei-cut in the dual relation to the routing path is introduced; this aids in both evaluation and proof.