A Study of Vacuum Efficiency for Silicon on Insulator Wafers

Bacquian, Bryan Christian S.; Gomez, Frederick Ray I.

doi:10.9734/jerr/2019/v6i116936

Cited by 5 publications

(8 citation statements)

References 6 publications

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“…SOI wafers are measured prior wafer taping process and was observed to have the edge area 30 microns (µm) thinner than the device, with warpage measurement in Fig. 2 of about 0.5 mm around the edge area [4].…”

Section: Silicon-on-insulator Wafermentioning

confidence: 99%

“…Furthermore, wafer flatness is dependent on the amount of wafer clamp vacuum pressure and helps compensate wafer warpage during backgrinding process. The vacuum source pressure must be identical to wafer clamp vacuum, else, vacuum leakage would happen [4].…”

Section: Chuck Table Designmentioning

confidence: 99%

“…Source: Bacquian and Gomez [4] The wafer exhibits a scratch pattern on the backside after backgrinding process as shown in Fig. 4.…”

Section: Fig 3 Typical "Frowning" Warpagementioning

confidence: 99%

“…Source: Bacquian and Gomez [4] special process should be considered in making an outer circumference lip, where no grinding pressure is applied on the edge of the wafer during backgrinding. Discussion shared in [11][12][13] on critical processes such as wafer saw, are helpful to mitigate or eliminate defects associated with assembly manufacturing.…”

Section: Fig 6 Vacuum Error On the Robot Armmentioning

confidence: 99%

“…Wafer edge chipping and warpageSource: Bacquian and Gomez[6] Back side image of the wafer Source: Bacquian and Gomez[4] …”

mentioning

confidence: 99%

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A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

Bacquian¹,

Gomez²

2020

JERR

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The relentless advancement and trends on thinner packages have become the focus in the semiconductor manufacturing industry. The requirement of thinner packages also demands a thinner vertical structure of the semiconductor electronic design. As a major contributor on the vertical structure of the electronic package, die or wafer is also essential to go thinner. As the wafer becomes thinner, various problems may occur during transport and even the backgrinding process itself. Wafer warpage is one of the main concerns during the wafer backgrinding process. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poor grinding and broken wafer. Wafer backgrinding stress and backgrinding tape tension also contribute to the effect on wafer warpage. Challenges exist in processing different silicon wafer technology, particularly the silicon-on-insulator (SOI) technology. Evaluating the effect of backgrinding tape selection and vacuum efficiency to eliminate such warpage is presented in this paper.

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Section: Silicon-on-insulator Wafermentioning

confidence: 99%

Section: Chuck Table Designmentioning

confidence: 99%

“…Source: Bacquian and Gomez [4] The wafer exhibits a scratch pattern on the backside after backgrinding process as shown in Fig. 4.…”

Section: Fig 3 Typical "Frowning" Warpagementioning

confidence: 99%

Section: Fig 6 Vacuum Error On the Robot Armmentioning

confidence: 99%

“…Wafer edge chipping and warpageSource: Bacquian and Gomez[6] Back side image of the wafer Source: Bacquian and Gomez[4] …”

mentioning

confidence: 99%

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A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

Bacquian¹,

Gomez²

2020

JERR

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Wafer Tape Selection Analysis for Adhesion Problem Mitigation

Bacquian¹,

Gomez²

2019

JERR

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Wafer passivation or the protective layer of the internal circuitry of the die plays a major role of providing protection and the isolation of electrical stability of the active circuit on the top area of the wafer. Passivation is normally a screen of an oxide layer on the surface of the silicon wafer or the carrier of internal circuitry of the die. Passivation is normally in the form of polyimide or a glass material. From the wafer structure, it is important to cover the active circuit to ensure no other noises will be induced to the wafer. Inclusion of the passivation layer will help maximize the functionality of the semiconductor device thus eliminating noises coming from the external sources. As the integrated circuit (IC) package goes thinner, the requirement of having the active circuit or the die thinner is the main concern during the wafer preparation process. Wafer backgrinding or wafer thinning is the focal process involved to satisfy such requirement. Prior performing the wafer thinning process, the application of tape, normally in a form of polyolefin or polyvinyl chloride should be performed to eliminate contamination and protects the active layer of the wafer during the process. However, there should be enough adhesion between the wafer and the thinning tape itself. High adhesion strength may lead to adhesive remains or worst, passivation will be peeled off from the active layer of the wafer. Adhesion to the passivation layer should be properly evaluated and monitored in such way that will eliminate adhesive remains during detaping process after wafer thinning. The effect of adhesion strength could be predicted by properly selecting thinning or protective tape to be used. Higher adhesion strength could be achieved but due to criticality of passivation to tape adhesion, ultra-violet (UV) process should be included to substantially decreased the adhesion. The importance of UV exposure is also discussed on this paper.

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Laser DAF Cut Augmentation for Thin Wafers

Bacquian¹,

Gomez²

2020

JERR

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The semiconductor industry is becoming more inclined to thinner integrated circuit (IC) packages. Thinner packages with thin wafer or die prefer the die attach film (DAF) technology as the die adhesive material solution. As the wafer goes thinner, it becomes more of a challenge in process development, especially during its assembly preparatory stages. As the dies become smaller and thinner, wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality. New technologies were developed and introduced in the industry and one of this is the laser die attach film (DAF) cutting. The method was developed together with dies before grinding (DBG) as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw. This paper discusses the laser DAF cut development covering the design of experiments (DOE) to understand the different characteristics of laser DAF solution. Validations are made through actual simulation and wafer processing. The paper also covers the interaction of different DAF thicknesses and parameters in order to define the critical characteristics in achieving optimal DAF cutting process responses.

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A Study of Vacuum Efficiency for Silicon on Insulator Wafers

Cited by 5 publications

References 6 publications

A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

Wafer Tape Selection Analysis for Adhesion Problem Mitigation

Laser DAF Cut Augmentation for Thin Wafers

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