A Study on Copper Pillar Interconnect in Flip-Chip-On-Module Packaging

Huang, Mingliang; Yeow, Ong Gee; Poo, Chia Yong; Jiang, T.

doi:10.1109/eptc.2007.4469775

Cited by 6 publications

(6 citation statements)

References 5 publications

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“…[6][7][8] A widely adopted bonding scheme for 3D integration is to add a thin Sn-based solder layer on top of Cu pillar bumps. [9][10][11][12] It is thus expected that the mechanical behavior of 3D bonded chips=wafers will be considerably different from that of chips=wafers subjected to conventional flip-chip bonding.…”

Section: Introductionmentioning

confidence: 99%

“…[13][14][15][16] To suppress the Cu=Sn reaction, the adoption of electroless Ni(P) as a diffusion barrier layer has been investigated. 11,[17][18][19][20] However, according to a studies carried out by Wang and Liu, Ni out-diffusion from the barrier caused the deterioration of the barrier, which led to a drop in bonding strength. 21,22) We previously reported the mechanism of the thermal degradation of a Ni(P) barrier at high temperatures (250-350 °C).…”

Section: Introductionmentioning

confidence: 99%

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Thermal reliability of a bilayer of Ni(P)/Cu as a diffusion barrier for Cu/Sn/Cu bonding

Lee

Jeon

Gan

et al. 2016

Jpn. J. Appl. Phys.

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This study examines the effects of barrier layers on the aging behavior of Cu/Sn bonding for three-dimensional (3D) integration. We compare the behavior of different bonding structures [Cu/Sn with no barrier, Ni(P) barrier, and Ni(P)/Cu bilayer barrier] after aging samples at 150 °C for long durations (up to 900 h). While the samples with no barrier allowed extensive Cu diffusion and the formation of Kirkendall voids, the Ni(P) barrier samples broke down as Ni outdiffused into the Sn layer. The bilayer barrier samples demonstrated excellent aging stability with the thin Ni(P)/Cu bilayer effectively suppressing Ni outdiffusion.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Thermal reliability of a bilayer of Ni(P)/Cu as a diffusion barrier for Cu/Sn/Cu bonding

Lee

Jeon

Gan

et al. 2016

Jpn. J. Appl. Phys.

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“…1) The advantages of copper pillar bumping include higher interconnecting densities, higher reliability, improved electrical and thermal performances with the potential for lead-free bump implementation. [2][3][4] In fine pitch flip chip application, copper pillar bumps are usually fabricated by using photolithography and electroplating. How to choose proper photoresist is important, which can assist us to obtain high aspect-ratio and fine-pitch mold for electroplating.…”

Section: Introductionmentioning

confidence: 99%

High Coplanarity and Fine Pitch Copper Pillar Bumps Fabrication Method

Huang

Hsu

Lee

et al. 2010

Jpn. J. Appl. Phys.

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In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the uniformity in wafer (UIW) could be sharply improved from 4.31% after plating to 2.88% after polishing and even to 2.54% after reflow throughout the entire 4 inch wafer.

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“…A practical interconnect structure currently used has a reflowable solder cap on copper pillars. 5,9 Wang et al used high aspect ratio copper pillars to improve the I/O density. 9 The use of a solder cap on the pillar avoided the high-temperature copper-to-copper fusion process.…”

mentioning

confidence: 99%

“…5,9 Wang et al used high aspect ratio copper pillars to improve the I/O density. 9 The use of a solder cap on the pillar avoided the high-temperature copper-to-copper fusion process. However, the electrical and mechanical limitations of solder still exist, including brittle intermetallics, poor electromigration resistance, and large chemical footprint.…”

mentioning

confidence: 99%

Fabrication and Thermo-Mechanical Characterization of Fine Pitch All-Copper Interconnect

Saha

Koo

et al. 2012

J. Electrochem. Soc.

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The thermal cycling and effect of misalignment of all-copper, chip-to-substrate bonding was evaluated. Electroplated copper pillars on the chip and board were joined using an optimized electroless deposition process after alignment. The width of the copper lines were 50, 25 and 15 μm The joints were robust and void-free. The mechanical strength and electrical continuity of the bonded copper pillars were assessed before and after thermal cycling. The mechanical strength of these joints was substantially higher than typical solder fracture strength. Finite element medeling was used to analyze the effect of (i) misalignment and (ii) underfill on the mechanics of the assembled parts.

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A Study on Copper Pillar Interconnect in Flip-Chip-On-Module Packaging

Cited by 6 publications

References 5 publications

Thermal reliability of a bilayer of Ni(P)/Cu as a diffusion barrier for Cu/Sn/Cu bonding

Thermal reliability of a bilayer of Ni(P)/Cu as a diffusion barrier for Cu/Sn/Cu bonding

High Coplanarity and Fine Pitch Copper Pillar Bumps Fabrication Method

Fabrication and Thermo-Mechanical Characterization of Fine Pitch All-Copper Interconnect

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