A Study on Practically Unlimited Endurance of STT-MRAM

Kan, Jimmy J.; Park, Chando; Ching, Chi; Ahn, Jaehwan; Xie, Yuan; Pakala, Mahendra; Kang, Sungwon

doi:10.1109/ted.2017.2731959

Cited by 77 publications

(36 citation statements)

References 16 publications

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“…However, flash memory suffers from physical limitations in its fabrication process and reliability problems [ 2 , 3 ]. Therefore, next-generation memories such as magnetoresistive random access memory (MRAM) [ 4 ], ferroelectric random access memory (FeRAM) [ 5 ], phase–change random access memory (PCRAM) [ 6 ], and resistive random access memory (ReRAM) [ 7 , 8 ], are being widely developed to replace flash memory devices. Among these memory types, ReRAM is the most promising NVM [ 9 ].…”

Section: Introductionmentioning

confidence: 99%

Impact of Electrode Surface Morphology in ZnO-Based Resistive Random Access Memory Fabricated Using the Cu Chemical Displacement Technique

You

Lin

et al. 2018

Materials

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Electrochemical-metallization-type resistive random access memories (ReRAMs) show promising performance as next-generation nonvolatile memory. In this paper, the Cu chemical displacement technique (CDT) is used to form the bottom electrode of ReRAM devices. Compared with conventional deposition methods, the Cu-CDT method has numerous advantages for ReRAM fabrication, including low cost, low temperature fabrication, and the provision of unconsolidated Cu film and large surface roughness. Moreover, the Cu-CDT method is a favorable candidate for overcoming the Cu etching problem and is thus suitable for fabricating ReRAM devices. Using this technique, the surface morphology of a thin Cu film can be easily controlled. The obtained results show that the electric fields during the Forming and SET operations decreased, and the on-state current increased in the RESET operation, as the Cu-CDT displacement time was increased. The Cu-CDT samples exhibited a low operation field, large memory window (>106), and excellent endurance switching cycle characteristics. Moreover, this paper proposes a model to explain the electrical characteristics of ReRAM, which are dependent on the surface morphology.

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Section: Introductionmentioning

confidence: 99%

Impact of Electrode Surface Morphology in ZnO-Based Resistive Random Access Memory Fabricated Using the Cu Chemical Displacement Technique

You

Lin

et al. 2018

Materials

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“…However, STT-MRAM has shown high potential in scalability, as reported in ref. [99], fast switching speed [100], and almost unlimited cycling endurance [101,102]. Figure 11g shows the MIM stack of FeRAM, where an insulating layer based on a ferroelectric (FE) material, typically in doped HfO 2 [103] or perovskite materials [104,105], is sandwiched between two metal electrodes.…”

Section: Memristive Devices With 2-terminal Structurementioning

confidence: 99%

Memristive and CMOS Devices for Neuromorphic Computing

et al. 2020

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Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

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“…The reduction of device area A in p-STT-MRAM devices allows to decrease the switching current, which is required to minimize the cell area limited by the driving transistor in 1T-1MTJ structures [14], [19]. In addition to reducing the footprint and power consumption, area scaling also allows to improve cycling endurance due to the Poisson area scaling of TDDB [14], [18]. To study the area dependence, Fig.…”

Section: Area Dependencementioning

confidence: 99%

“…13(b) for various A, indicating an areaindependent Weibull shape factor η = 1.35 in the formula log(-log(1-F) = ηlog (N C /N C0 ). Such a value of the shape parameter η can be explained by intrinsic TDDB processes, such as defect generation controlled by the electrical stress, in contrast to extrinsic breakdown processes for η < 1 [14], [34]. From Poisson area scaling, we calculate a theoretical Corresponding Weibull plot for measured and calculated N C .…”

Section: Area Dependencementioning

confidence: 99%

“…To drive the switching current across the MTJ, bipolar voltage pulses are applied, which might induce degradation and time-dependent dielectric breakdown (TDDB) in the long term. Although the cycling endurance of STT-MRAM is generally referred to as virtually infinite [14], the repeated electrical stress during cycling induces a breakdown-limited endurance lifetime, which poses a limitation on the applicability of STT-MRAM as working memory or in-memory computing element. Despite the relevant need for high endurance, the characterization methodology, the physical understanding, and the simulation models for breakdown-limited endurance are not yet well established.…”

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Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

Carboni

Ambrogio

Chen

et al. 2018

IEEE Trans. Electron Devices

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Perpendicular spin-transfer torque (p-STT) magnetic memory is gaining increasing interest as a candidate for storage-class memory, embedded memory, and possible replacement of static/dynamic memory. All these applications require extended cycling endurance, which should be based on a solid understanding and accurate modeling of the endurance failure mechanisms in the p-STT device. This paper addresses cycling endurance of p-STT memory under pulsed electrical switching. We show that endurance is limited by the dielectric breakdown of the magnetic tunnel junction stack, and we model endurance lifetime by the physical mechanisms leading to dielectric breakdown. The model predicts STT endurance as a function of applied voltage, pulsewidth, pulse polarity, and delay time between applied pulses. The dependence of the endurance on sample area is finally discussed. Index Terms-Cycling endurance, magnetic tunnel junction (MTJ), reliability analysis, reliability modeling, spintransfer torque magnetoresistive RAM (STT-MRAM). I. INTRODUCTION M AGNETORESISTIVE random access memory (MRAM) is one of the most promising memory technology due to its fast switching, nonvolatile states, high endurance, CMOS compatibility, and low current operation [1]. Thanks to these characteristics, MRAM is under intense consideration for applications as storageclass memory (SCM) [2]-[5] and embedded nonvolatile

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A Study on Practically Unlimited Endurance of STT-MRAM

Cited by 77 publications

References 16 publications

Impact of Electrode Surface Morphology in ZnO-Based Resistive Random Access Memory Fabricated Using the Cu Chemical Displacement Technique

Impact of Electrode Surface Morphology in ZnO-Based Resistive Random Access Memory Fabricated Using the Cu Chemical Displacement Technique

Memristive and CMOS Devices for Neuromorphic Computing

Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

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