2008 IEEE Custom Integrated Circuits Conference 2008
DOI: 10.1109/cicc.2008.4672026
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A study on process-compatibility in CMOS-first MEMS-last integration

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Cited by 7 publications
(4 citation statements)
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“…This implies that one would need to consult with a pre-calibrated look-up table to speculate the voltage level needed to attain the target scan angle. It is rather recommended, therefore, that the scanner angle would be controlled by the PWM of narrow pulse width (duty ratio < 10%) at a given voltage level, as the drive circuit can be simply assembled with a compact digital electronics with a level shifter circuit (19) .…”
Section: Verification Of Pwm Operationmentioning
confidence: 99%
“…This implies that one would need to consult with a pre-calibrated look-up table to speculate the voltage level needed to attain the target scan angle. It is rather recommended, therefore, that the scanner angle would be controlled by the PWM of narrow pulse width (duty ratio < 10%) at a given voltage level, as the drive circuit can be simply assembled with a compact digital electronics with a level shifter circuit (19) .…”
Section: Verification Of Pwm Operationmentioning
confidence: 99%
“…Along with the ever-growing demand for miniaturized sensors and actuators, interest is also sharply increasing toward fully monolithic systems, enabling the integration of microelectromechanical systems (MEMS) and electronics directly onto a single integrated circuit (IC) [1][2][3][4][5][6][7]. These highly integrated solutions can provide numerous advantages over discrete or system-in-package (SiP) implementations: (1) The inclusion of IC and MEMS within a common batch fabrication flow can reduce costs through the consolidation of certain process steps, in addition to the sharing of manufacturing equipment, materials and facilities.…”
Section: Benefits and Types Of Monolithic Integrationmentioning
confidence: 99%
“…14) Figure 1(b-2) shows another method by which a MEMS sensor is fabricated on a silicon-on-insulator (SOI) wafer by etching a silicon layer and a buried oxide (BOX) layer from the top surface of the wafer. [15][16][17][18][19][20][21][22][23] In the case of the method shown in Fig. 1(b-1), it is easy to fabricate devices on a silicon wafer.…”
Section: Introductionmentioning
confidence: 99%