A study on substrate noise coupling among TSVs in 3D chip stack

Abstract

A map of Si substrate noise from through-silicon vias (TSVs) is presented by measurement of real stacked test vehicle. A 65 nm CMOS test chip is manufactured and integrated by die-to-die bonding. The stacked test chip is packaged with an organic interposer and mounted on an evaluation board. A thinned Si substrate is excited through V DD and V SS TSVs of noise source circuitry and the noise waveforms are captured by an on-chip evaluation circuitry with 2D mapped probe point on the substrate. The result shows overlapped noise waveforms that as its placement, due to voltage division with Si substrate resistance. A simple Si substrate model is created and employed for first analysis. An analytical result explains measurement result qualitatively including the noise overlapping and cancelling on the Si substrate.

A compact 2-18GHz ultra-wideband frequency-conversion T/R module based on a 3D heterogeneous integrated process

“…However, these designs still employ a two-dimensional (2D) multichip module (MCM) package, the minimum sizes of which are limited by the sizes of the applied chips. To address this issue, an increasing number of researchers are employing three-dimensional (3D) packaging to achieve high integration of frequency-conversion modules and T/R modules [21][22][23][24][25][26], aiming to break the chip size limit with chip stacking in the third dimension.…”

Wideband transmission optimization for heterogenous interconnection in 3D IC

“…However, the noise coupling and signal integrity problems in 3D high density transmissions bring extra insert losses [13,14,15,16,17,18]. Different methods are proposed to improve the transmissions performance of redistribution layer (RDL) and TSV, such as meta surface technology [19], via bottom cleaning [20], TSV defect tolerance [21], siliconcore coaxial TSV [22], quasi-coaxial TSV [23,24], PN junction and shielding TSV [25,26], differential channel [27], inductive impedance optimization [28].…”

Analysis and evaluation of noise coupling between through-silicon-vias

“…Through-silicon-vias (TSVs), the biggest feature of 3D-SICs, enable vertical signal transfer among stacked ICs which enhances performance and energy by optimized signal lines between stacked ICs [8][9][10][11][12][13]. Although wider signal bus is required for enormous scale data transfer, densely manufactured signal bus needs to solve crosstalk among the channels [14][15][16][17][18][19][20] as well as power line noise [21][22][23][24][25][26][27]. To avoid bit error caused by such crosstalk, it requires frequency or voltage optimization that cause additional issues like lower data transfer speed or larger power consumption, respectively [28,29].…”