A Study on the Programming Structures for RRAM-Based FPGA Architectures

Optimization opportunities in RRAM-based FPGA architectures

“…Previous works [1]- [6] focus on replacing Static Random Access Memory (SRAM)-based multiplexers in the classical FPGA architectures with RRAM-based multiplexers. Since RRAM-based multiplexers are naturally more delay-efficient than SRAM-based multiplexers, RRAM-based FPGAs can achieve a 7%-15% gain in area, a 45%-58% reduction in delay and a 20%-58% reduction in power, when compared to SRAM-based FPGAs [1]- [4].…”

“…CBs connect routing tracks to CLB inputs, while SBs interconnect routing tracks. Advancements in RRAM technology have attracted intensive research efforts on replacing SRAM-based routing multiplexers with RRAMbased implementations [1]- [6]. When a RRAM is programmed to LRS/HRS, it propagates/blocks signals, similarly to a transmission gate in on/off state.…”

“…More details about RRAM technology can be found in [9]. Previous works [1]- [6] predicted that using RRAM-based multiplexers, FPGAs can benefit from a 7%-15% area reduction, a 45%-58% performance improvement, and a 20%-58% power saving, as compared to SRAMbased counterparts. However, these improvements are obtained by simply replacing the SRAM-based multiplexers in classical FPGA architectures with RRAM-based multiplexers.…”

“…In addition, most RRAM-based researches overlook the challenges in physical designs, i.e., consider a ideal RRAM, which may cause architecture-level improvements less realistic. Recent work [6] has carefully studied the physical design details of RRAM programming structures, and proposes an efficient 4T(ransistor)1R(RAM) programming structure. Therefore, it is worthy to investigate the architectural enhancements for RRAM-based FPGAs, by considering realistic RRAM-based multiplexer designs.…”

“…We consider a two-level structure for the SRAM-based multiplexers because it guarantees the best area-delay product compared to one-level or multi-level structures [10]. The RRAM-based multiplexer is built with a one-level structure and 4T1R programming elements exploiting I/O transistors [6]. Note that, in a RRAM-based multiplexer, programming structures are efficiently shared by the RRAMs.…”