A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection

Takagi, Kenta; Mizuno, Kosuke; Izumi, Shintaro; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.1109/icassp.2013.6638112

Cited by 26 publications

(22 citation statements)

References 10 publications

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“…This design can process 1080HD video at 60 fps, with total power consumption of 45.3 mW at a supply voltage of 0.72V. Although this work supports multiscale detection, its energy per pixel is less than the single scale detector reported in [9] and on-chip memory size is only 0.538 Mbit.…”

Section: Hardware Complexitymentioning

confidence: 94%

“…In [6], HOG-based detector is implemented on an FPGA and can process 1080HD (1920×1080 pixels) at 30 fps with a single scale support. An ASIC version of this design is presented in [9] with dual cores to enable voltage scaling down to 0.7 V with power consumption of 40.3mW for 1080HD at 30 fps. In [5], the detector is implemented on an FPGA and can process 1080HD at 64 fps multi-scale support by time-multiplexing 18 scales across 3 successive frames.…”

Section: Previous Workmentioning

confidence: 99%

“…In [5], the detector is implemented on an FPGA and can process 1080HD at 64 fps multi-scale support by time-multiplexing 18 scales across 3 successive frames. It should be noted that these implementations have relatively large on-chip memory requirements (e.g., [9] Fig. 2 shows a block diagram of the steps involved in object detection using HOG features.…”

Section: Previous Workmentioning

confidence: 99%

“…All calculations that include the HOG feature must be completed before it is thrown away. Accordingly, the SVM classification, which involves a dot product between HOG features and SVM weights, is done using an on-the-fly approach similar to [9].…”

Section: ) Hog Feature Extractionmentioning

confidence: 99%

“…The pre-processing required for the gradient image detection architecture introduces very small area and power overhead. Table III presents a comparison between this work and the ASIC implementation in [9]. This design can process 1080HD video at 60 fps, with total power consumption of 45.3 mW at a supply voltage of 0.72V.…”

Section: Hardware Complexitymentioning

confidence: 99%

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Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support

Suleiman

Sze

2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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Abstract-In this paper, we present a real-time and energyefficient multi-scale object detector using Histogram of Oriented Gradient (HOG) features and Support Vector Machine (SVM) classification. Parallel detectors with balanced workload are used to enable processing of multiple scales and increase the throughput such that voltage scaling can be applied to reduce energy consumption. Image pre-processing is also introduced to further reduce power and area cost of the image scales generation. This design can operate on high definition 1080HD video at 60 fps in real-time with a clock rate of 270 MHz, and consumes 45.3 mW (0.36 nJ/pixel) based on post-layout simulations. The ASIC has an area of 490 kgates and 0.538 Mbit on-chip memory in a 45nm SOI CMOS process.

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Section: Hardware Complexitymentioning

confidence: 94%

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: ) Hog Feature Extractionmentioning

confidence: 99%

Section: Hardware Complexitymentioning

confidence: 99%

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Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support

Suleiman

Sze

2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images

Khan

Bilal

et al. 2016

VLSI-SoC: Design for Reliability, Security, and Low Power

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Pedestrian detection has lately attracted considerable interest from researchers due to many practical applications. However, the low accuracy and high complexity of pedestrian detection has still not enabled its use in successful commercial applications. In this chapter, we present insights into the complexity-accuracy relationship of pedestrian detection. We consider the Histogram of Oriented Gradients (HOG) scheme with linear Support Vector Machine (LinSVM) as a benchmark. We describe parallel implementations of various blocks of the pedestrian detection system which are designed for full-HD (1920x1080) resolution. Features are improved by optimal selection of cell size and histogram bins which have been shown to significantly affect the accuracy and complexity of pedestrian detection. It is seen that with a careful choice of these parameters a frame rate of 39.2 fps is achieved with a negligible loss in accuracy which is 16.3x and 3.8x higher than state of the art GPU and FPGA implementations respectively. Moreover 97.14% and 10.2% reduction in energy consumption is observed to process one frame. Finally, features are further enhanced by removing petty gradients in histograms which result in loss of accuracy. This increases the frame rate to 42.7 fps (18x and 4.1x higher) and lowers the energy consumption by 97.34% and 16.4% while improving the accuracy by 2% as compared to state of the art GPU and FPGA implementations respectively.

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Hardware implementation of real-time pedestrian detection system

Helali

Ameur

Górriz

et al. 2020

Neural Comput & Applic

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A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection

Cited by 26 publications

References 10 publications

Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support

Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support

A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images

Hardware implementation of real-time pedestrian detection system

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