A sub 100ns 256K DRAM

Abstract

A 256K X 1 DYNAMIC RAM using single or double polusilicon technology, low resistance poly interconnects and a 2p process w i i e d e s c r i b L F a u l t tolerant techniques, a nibble mode and a CAS before RAS refresh option will also be discussed.Single polysilicon has a processing advantage of simplicity for obtaining higher yields. The cell of Figure 1 shows the titanium silicide word line used for fast row access time. Potential punch-through problems of the transfer device have been reduced through process techniques. Double polysilicon eliminates the punch-through concerns, improves the capacitor size somewhat, but adds extra complexity in the process.The basic architecture was chosen for alpha particle immunity, speed, noise rejection and signal strength. Figure 2 is a die photo showing the row decoders down the center, driving minimum length word lines. Active restores and row line bootstraping allow full level storage t o improve the soft error rates. Metal bit lines are connected to a shared sense amplifier shown in Figure 3. The shared Sense amplifier has two key performance enhancements. First, the voltage signal strength is nearly double that of the non-shared sense amplifier. Second, the soft error rate due to bit line hits is reduced by nearly a factor of two. This is due to the electrical isolation of half of the memory from the sense amplifiers during the read cycle. A clock driver utilizing a multiple threshold process has been included in the DRAM. The simplicity of the circuit, shown in Figure 4, makes layout more efficient and reduces peak current transients when the clock is fired. spare elements should be required to give a significant improvement in yield. The entire memory has 8 spare row decoders Failure analysis on 64K DRAME has shown that only a few and 4 spare column decoders. Each spare row decoder drives a pair of row lines in each direction. Poly fuses are opened with a laser so there is n o speed penalty paid for redundancy. In addition, bad elements are removed from the circuit by fuses which fit in the array metal and poly pitch. Fuses were also used during the early phases of circuit development to tweak timing signals for optimizing performance.mode. An internal organization of 64K x 4 allows four bits of data to be presented to the output section simultaneously. A four-bit serial shift register enables the one-of-four output decoder logic, such that either reading or writing can occur at a 33MHz data rate which should suit a number of applications needing fast data rates. An oscilloscope waveform of the nibble access is shown in Figure 5. The first data access (50ns) is determined by the column access time. After that&data becomes valid every 15ns from the falling e a o f CAS-To obtain an on-chip refresh function, CAS before RAS t i m i n g x c enables the internal refresh addresses&mall, static CAS buffer is used to route the first major RAS signal to the e s s section or to the refreelogic but will not impact the RAS a d d r e e o l d time or the RAS access time. A lOns se...