A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

Abstract

This paper describes a low power Intel® Architecture (IA) processor specifically designed for Mobile Internet Devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) frontside-bus (FSB). The design contains 47 million transistors in a die size under 25 mm 2 manufactured in a 9-metal 45nm CMOS process. Thermal design power (TDP) consumption is measured at 2W, 1.0V, 90 o C using a synthetic power-virus test at a frequency of 1.86GHz.

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

“…The micro-benchmarks generated will be composed by an end-less loop of 4K instructions (lines 9-10). The instructions will be load vector instructions (lines [11][12][13][14][15][16][17] that hit equally to the three levels of the cache hierarchy (lines [18][19][20][21][22]. The registers and immediate operands of the instructions will be initialized to a constant value (lines [23][24][25][26] and the dependency distance between the instructions will be assigned randomly (lines [27][28][29].…”

“…The second, the POWER7 microarchitecture definition that provides the mapping between instructions and micro-architecture components stressed, is used in lines 14-16 of the example to select only the loads that stress the Vector Scalar Unit (VSU). The last functionality, the analytical set-associative cache model, is used to statically ensure a specific distribution among the memory hierarchy levels (lines [18][19][20][21][22]. The following sections present the details of these three main modules of the Architecture module.…”

“…Moreover, specifically designed benchmarks, named micro-benchmarks, are needed in several situations. For instance, they have been used to reverse engineer structure latencies [24] or branch organization [37,45], to evaluate performance, power or thermal efficiency [15,22,28,38] or to generate and calibrate models [8,9,12].…”

An energy case for hybrid datacenters

“…Companies such as Microsoft and Google are deploying new datacenters near cheap power sources to mitigate energy costs. Processor manufacturers are pursuing their roadmap of multi-core architectures [9] and low-power designs [14]. Several research proposals deal with power efficient designs and protocols for specific workloads [12], office environments [6,20] and high speed networks [19].…”

“…For example, the Atom processor [14] includes an in-order pipeline that can execute two instructions per cycle, a small L2 cache and power-efficient clock distribution. This results in a strongly reduced transistor count with low leakage power and limited power consumption at low load.…”