A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Bhavnagarwala, A.J.; Kosonocky, Stephen; Radens, C.; Chan, Yuen; Stawiasz, K.; Srinivasan, Uma; Kowalczyk, S. P.; Ziegler, Matthew M.

doi:10.1109/jssc.2008.917506

Cited by 87 publications

(25 citation statements)

References 22 publications

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“…7) Effect of Cell GND Boost as a Writeability Assist: GND boost weakens the cross-coupled inverters, improving writeability [13]. However, the effect of a large GND boost saturates after 30%, because the NMOS PG must pull the low internal node high for this assist to work, but can only pull up to around Vdd-V th .…”

Section: ) Effect Of Cell Vdd Collapse As a Writeability Assistmentioning

confidence: 99%

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Zimmer

Toh

et al. 2012

IEEE Trans. Circuits Syst. II

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Section: ) Effect Of Cell Vdd Collapse As a Writeability Assistmentioning

confidence: 99%

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Zimmer

Toh

et al. 2012

IEEE Trans. Circuits Syst. II

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“…The WSNM plots (Fig. 8) using read and write VTCs have only one root, assuring its functionality as a monostable circuit during write operation [17]. This is the indication of successful writing.…”

Section: E Write Static Noise Marginmentioning

confidence: 88%

Stability and variability enhancement of 9T SRAM cell for subthreshold operation

Anand

Pal

Islam

2014

2014 Annual IEEE India Conference (INDICON)

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This article presents a new way for designing a more reliable and variability resilient 9T SRAM cell which is based on DTMOS (dynamic threshold MOS) and CCBB (cell content body bias) technique under subthreshold operation. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional 9T SRAM cell. The proposed 9T SRAM cell shows 41.8% (9.5%) lower read access time (write access time) compared to conventional 9T SRAM cell. It also exhibits robustness by achieving narrower spread in read access time (write access time) by 53.01% (8%) compared to its conventional 9T SRAM cell. Moreover, the proposed bitcell offers 9.5% (47.4%) improvement in read static noise margin (write static noise margin) @ 350 mV.

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“…These include altering the voltages of the cell array (V DD , V SS ), wordline (WL), and bitline precharging devices to improve both RSNM and WM (e.g. [8]). However, we need to evaluate their efficacy in the target technology in order make the optimal choice for our design.…”

Section: Read/write Assist Evaluationmentioning

confidence: 99%

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

Nalam

Bhargava

Ringgenberg

et al. 2009

2009 IEEE International Conference on Computer Design

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-A designer's intent and knowledge about the critical issues and trade-offs underlying a custom circuit design are implicit in the simulations she sets up for design creation and verification. However, this knowledge is tightly conjoined with technology-specific features and decoupled from the final schematic in traditional design flows. As a result, this knowledge is easily lost when the technology specifics change. This paper presents a Technology Agnostic Simulation Environment (TASE), which is a tool that uses simulation templates to capture the designer's knowledge and separate it from the technologyspecific components of a simulation. TASE also allows the designer to form groups of related simulations and port them as a unit to a new technology. This allows an actual design schematic to remain tied to the analyses that illuminate the underlying trade-offs and design issues, unlike the case where schematics are ported alone. Giving the designer immediate access to the trade-offs, which are likely to change in new technologies, accelerates the re-design that often must accompany porting of complicated custom circuits. We demonstrate the usefulness of TASE by investigating Read and Write noise margins for a 6T SRAM in predictive technologies down to 16 nm. I. INTRODUCTIONThe rapid creation of new technologies according to Moore's Law has made cross-technology porting an important part of circuit design. An ideal method for porting custom circuits would reuse an existing design in a new technology while also re-optimizing or restructuring the design to best take advantage of that process's features. For complicated blocks that defy complete automation, the best way to do this would expose the tradeoffs and knowledge that underlie the original design in full view of the designer in the new technology. Existing methods for porting offer imperfect solutions. Classic ASIC flows approach porting by largely decoupling the design (e.g. HDL) from a specific technology. The foundry typically provides the process dependent part of the design flow (standard cell library), allowing for relatively easy porting. Custom circuits, on the other hand, require more careful designer intervention for process porting. A large number of tools exist for direct porting of custom layout (e.g. [1]), but these do not carry any useful design information to help a custom designer. To access design information, designers can use built-in SPICE features (.alter, .param, .lib) that allow single netlists to support multiple processes, but these features become unwieldy for complex designs or when reusing netlists for different simulations. Many designers employ their own scripts for porting designs and simulations, but these tend to be ad hoc, proprietary, or generally unavailable to the community.A large variety of optimization tools for analog circuits have been proposed, and some of these aid with process porting (e.g. [2]). The tool in [3] ports analog schematics and layout by identifying known sub-blocks (e.g. current mirror) and...

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A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Cited by 87 publications

References 22 publications

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Stability and variability enhancement of 9T SRAM cell for subthreshold operation

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

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