A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications

Abstract

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digitalto-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 µs at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional-N ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

“…The presented model is designed using the Verilog HDL and tested on FPGA. The terms such as power dissipation, power consumption and lockin time are computed to validate the efficiency of the suggested approach with existing models such as 2.4 GHz Low Power ADPLL (2.4 LPADPLL) [27], Variable Phase Accumulator (VPAC) [28], ADPLL with Optimized Digital Controlled Oscillator (ADPLL-ODCO) [29] ADPLL with Varactorless LC Digital Controlled Oscillator (ADPLL-VLCDCO) [30], Injection Locking Time to Digital Convertor based on Ring Oscillator (CFRO-ILTDC) [31], Fractional-N ADPLL (FNADPLL) [32], Bang-Bang Phase Frequency Detector (BB-PFD) [33] and Hybrid Phase Locked Loop (HPLL) [34].…”