A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control

Salem, Loai G.; Warchall, Julian; Mercier, Patrick P.

doi:10.1109/jssc.2017.2766215

Cited by 67 publications

(24 citation statements)

References 27 publications

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“…The calculation of figure of merit (FOM) is widely adopted by researchers and acts as a collective measure of all other performance parameters. The most established equation for calculating FOM is included in Equation (7), which is adopted by many researchers [19][20][21][22][23]45,47,48,[51][52][53][54][55][56][57][58]60,62]. Moreover, several methods of evaluating FOM is presented by authors to signify their design performances, which are added in Equation ( 8) [25], Equation (9) [44], Equation (10) [58], Equation (11) [59], Equation (12) [51], and Equation ( 13) [48].…”

Section: Figure Of Merit (Fom)mentioning

confidence: 99%

“…An unprecedented design approach for a recursive digital low-dropout regulator (RDLDO), shown in Figure 25, demonstrates the potential for an optimal response time and improved load regulation range compared with the previous design [53]. This design utilizes a successive approximation (SAR) algorithm, Sub-LSB pulse width modulation (PWM) duty control technique, and proportional derivative (PD) compensation scheme to ensure a befitting substitution of analog LDOs.…”

Section: Proportional Derivative (Pd) Compensation and Sub-lsb Duty Controlmentioning

confidence: 99%

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CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

et al. 2022

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Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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Section: Figure Of Merit (Fom)mentioning

confidence: 99%

Section: Proportional Derivative (Pd) Compensation and Sub-lsb Duty Controlmentioning

confidence: 99%

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

et al. 2022

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“…Consequently, the clock generation unit should be included in the D-LDO design. In contrast to conventional D-LDO architectures [9][10][11] as well as the hybrid schemes [12] that are oriented for high efficient regulation at sub-watt applications, there is limited literature available on D-LDO designs applicable to ultra-low power IoT systems by implementing integrated oscillator [13][14][15]. Such integration offers the advantage that coarse and fine regulation is not dependent on the operation of an external clock generation unit.…”

Section: Introductionmentioning

confidence: 99%

A Nano-Power 0.5 V Event-Driven Digital-LDO with Fast Start-Up Burst Oscillator for SoC-IoT

Konstantopoulos

Ussmueller

2020

JLPEA

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Towards the integration of Digital-LDO regulators in the ultra-low-power System-On-Chip Internet-of-Things architecture, the D-LDO architecture should constitute the main regulator for powering digital and mixed-signal loads including the SoC system clock. Such an implementation requires an in-regulator clock generation unit that provides an autonomous D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the oscillating frequency, this work presents a design with nano-power consumption, fabricated with an active area of 0.035 mm2 at a 55-nm Global Foundries CMOS process that introduces a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of D-LDO frequency. In combination with linear search coarse regulation and asynchronous fine regulation, it succeeds 558 nA minimum quiescent current with CL 75 pF, maximum current efficiency of 99.2% and 1.16x power efficiency improvement compared to analog counterpart oriented to SoC-IoT loads.

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“…Additionally, prior works using a multi‐weighted power stage [3] to ensure a balance in resolution and speed has a fluctuation of V OUT depending on how the weight is set. Although SAR‐based DLDO [6] can remove the trade‐off relationship between the resolution and transient response by using the structure of binary‐weighted PMOS array, adequate recovery time must be guaranteed to avoid a logic failure. In other words, its array is binary‐weighted, so the transient speed is determined by the target resolution and clock cycle, but the possible clock speed is limited by the recovery time.…”

Section: Introductionmentioning

confidence: 99%

“…Because the digital controller [1] works in sync with the clock, the response time is determined by the clock frequency, resulting in a trade-off relationship between the power dissipation and the speed of the feedback loop. Many state-of-the-art designs have been proposed to overcome the shortcoming [2][3][4][5][6]. The asynchronous controller using voltage-controlled oscillators (VCOs) [2] achieves a moderate transient performance even with a small output capacitance (C OUT ) of 40 pF.…”

mentioning

confidence: 99%

Digital LDO regulator with analogue‐assisted loop using source follower

Kim

2020

Electron. lett.

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A digital low-dropout regulator (DLDO) with an analogue-assist (AA) loop using a source follower has been proposed to improve the drawbacks of the DLDO. The proposed AA loop, which uses a source follower structure to generate the compensation current without additional passive components, mitigates the voltage droop and accelerates the transient response by complementing a slow digital control loop. Additionally, the boost loop enhances the deceleration of the compensation speed owing to the size of the power transistors. This ultimately results in the improvement of the transient response to the voltage droop side. Also, this can facilitate in reducing the amount of the output capacitance (C OUT) closely associated with the output voltage droop (ΔV OUT). The proposed DLDO occupying an area of 0.015 mm 2 is designed in a 28-nm CMOS process. The ΔT s of 14 ns with C OUT of 10 pF is achieved under the load step of 1.5-30 mA with edge time of 2 ns. The consumed quiescent current is 35 μA, and the figure-of-merit of 0.008 ps is achieved.

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A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control

Cited by 67 publications

References 27 publications

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

A Nano-Power 0.5 V Event-Driven Digital-LDO with Fast Start-Up Burst Oscillator for SoC-IoT

Digital LDO regulator with analogue‐assisted loop using source follower

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