A super-junction SOI-LDMOS with low resistance electron channel

Abstract

A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance (R on,sp) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage (BV) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R on,sp of the device can reach 253 V and 15.5 mΩ ⋅ cm2, respectively, and the Baliga’s figure of merit (FOM = BV 2/R on,sp) of 4.1 MW/cm2 is achieved, breaking through the silicon limit.

Review of the SiC LDMOS power device

“…Numerous investigations have demonstrated that the maximum electric field in LDMOS power devices is predominantly concentrated at the drain side adjacent to the gate edge. This highlights that this particular point is highly susceptible to high drain voltage [38][39][40][41][42][43] . Therefore, to increase the breakdown voltage, it becomes imperative to mitigate the peak electric field and achieve a more uniform surface electric field.…”