A superblock-based flash translation layer for NAND flash memory

Kang, Jeong‐Uk; Jo, Hang-Hyun; Kim, Jin-Soo; Lee, Joonwon

doi:10.1145/1176887.1176911

Cited by 279 publications

(126 citation statements)

References 3 publications

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“…Although it can achieve a good overall performance for both read and write operations, it requires a large amount of memory space to maintain the entire mapping table [15], [16]. As an example, 1 TB of a flash-based storage device requires 4GB of memory space only for the mapping table (assuming a 2KB page and 8 bytes per mapping entry).…”

Section: Address Mapping Schemes In Flash Memorymentioning

confidence: 99%

“…For fair evaluation, we assign the same number of mapping entries (4,096) for the cached mapping tables in SRAM and use the same size of cache memory (16KB) for both tier-1 index table in CFTL and Global Translation Directory (GTD) in DFTL. We additionally assume that the SRAM is sufficient enough to store the address mapping table for both FAST and AFTL, and approximately 3% of entire space is assigned for log blocks in FAST (this is based on [16]). Various types of workloads including real trace data sets are employed for more objective evaluations (Table 2).…”

Section: Evaluation Setupmentioning

confidence: 99%

“…6) Memory (SRAM) Consumption: For simplification, we assume the entire flash size is 4GB and each mapping table in the SRAM consists of 2,048 mapping entries. We also assume that approximately 3% of the entire space is allocated for log blocks in hybrid FTLs (this is based on [16]). …”

Section: ) the Number Of Block Erasementioning

confidence: 99%

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A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

Park

Debnath

2016

IEICE Trans. Inf. & Syst.

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SUMMARYThe Flash Translation Layer (FTL) is a firmware layer inside NAND flash memory that allows existing disk-based applications to use it without any significant modifications. Since the FTL has a critical impact on the performance and reliability of flash-based storage, a variety of FTLs have been proposed. The existing FTLs, however, are designed to perform well for either a read intensive workload or a write intensive workload, not for both due to their internal address mapping schemes. To overcome this limitation, we propose a novel hybrid FTL scheme named Convertible Flash Translation Layer (CFTL). CFTL is adaptive to data access patterns with the help of our unique hot data identification design that adopts multiple bloom filters. Thus, CFTL can dynamically switch its mapping scheme to either page-level mapping or block-level mapping to fully exploit the benefits of both schemes. In addition, we design a spatial locality-aware caching mechanism and adaptive cache partitioning to further improve CFTL performance. Consequently, both the adaptive switching scheme and the judicious caching mechanism empower CFTL to achieve good read and write performance. Our extensive evaluations demonstrate that CFTL outperforms existing FTLs. In particular, our specially designed caching mechanism remarkably improves the cache hit ratio, by an average of 2.4×, and achieves much higher hit ratios (up to 8.4×) especially for random read intensive workloads.

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Section: Address Mapping Schemes In Flash Memorymentioning

confidence: 99%

Section: Evaluation Setupmentioning

confidence: 99%

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A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

Park

Debnath

2016

IEICE Trans. Inf. & Syst.

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“…Some designs use a block-level mapping, sometimes with mechanisms that avoid a read-modify-write cycle on every random write [18,16]. Kang et al [15] partition the sector space into super-blocks that are mapped into erase-block groups; each group contains data blocks and log blocks that are merged once in a while. LAST uses a block-level map-ping for most of the data and a page-level mapping for a small subset of the data [19].…”

Section: Related Workmentioning

confidence: 99%

Prototyping a high-performance low-cost solid-state disk

Budilovsky

Toledo

Zuck

2011

Proceedings of the 4th Annual International Conference on Systems and Storage

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We present a design for a high-performance low-cost solid-state disk (SSD). Ignoring garbage-collection costs, our SSD performs only 1 + ε physical accesses to NAND flash pages for every request of a page-size block by the host, for some small ε. This is true for all access patterns, including random writes, which are usually slow on low-cost SSDs. Garbage collection in all SSDs is determined primarily by how full the SSD is, and its cost is similar in most SSDs. The unique feature in our design is that it achieves high performance even with when the SSD contains only a small amount of RAM. In most SSD designs, this would imply low performance; in ours, it does not. A small RAM lowers the cost of an SSD with a given flash array. Our design achieves high performance with a small RAM using two innovative ideas. One is the use of a clever mapping data structure. The second is a host-assisted hinting mechanism that uses RAM on the host to compensate for the small amount of RAM within the SSD. This mechanism is implemented as an enhanced SCSI driver (kernel module). Our prototyping methodology is also a significant contribution. We simulate the SSD in software, using files to represent the flash array, but the resulting prototype is a working SCSI device that file systems can be mounted on.

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“…However, since the SSD is in a low power state, it takes a wakeup time, T wakeup to make a state transition to the active state. Thus, the read operations start at time t 16 after the wakeup delay. Fig.…”

Section: Trace-based Simulation Of Performance Power and Dpm Policymentioning

confidence: 99%

Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems

Park

Yoo

Lee

et al. 2009

Software Technologies for Embedded and Ubiquitous Systems

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Abstract.Power consumption now becomes the most critical performance limiting factor to solid state disk (SSD) in embedded systems. It is imperative to devise design methods and architectures for power efficient SSD designs. In our work, we present the first step towards low power SSD design, i.e., power estimation of SSD. We present a practical approach of SSD power estimation which tries to keep the advantage of real measurement, i.e., accuracy, while overcoming its limitations, i.e., long execution time and lack of repeatability (and high cost) by a trace-based simulation. Since it is based on real measurements, it takes into account the power consumption of SSD controller as well as that of Flash memories. We show the effectiveness of the presented method in designing a dynamic power management policy for SSD.

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A superblock-based flash translation layer for NAND flash memory

Cited by 279 publications

References 3 publications

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

Prototyping a high-performance low-cost solid-state disk

Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems

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