“…, G p of the edges of the embedded graph G in the proof of Theo- Floorplanning is a fundamental issue in circuit layout [106,43,69,62,51,108,32,8,17,58,24,57,91,68,84,4]. Motivated by VLSI physical design, various representations of floorplans were proposed [110,109,33]. Designing a floorplan to meet a certain criterion is NP-complete in general [87,44,100], so heuristic techniques such as simulated annealing [102,101,17] are practically useful.…”