2007
DOI: 10.1093/ietfec/e90-a.4.823
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A Surjective Mapping from Permutations to Room-to-Room Floorplans

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Cited by 6 publications
(4 citation statements)
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“…, G p of the edges of the embedded graph G in the proof of Theo- Floorplanning is a fundamental issue in circuit layout [106,43,69,62,51,108,32,8,17,58,24,57,91,68,84,4]. Motivated by VLSI physical design, various representations of floorplans were proposed [110,109,33]. Designing a floorplan to meet a certain criterion is NP-complete in general [87,44,100], so heuristic techniques such as simulated annealing [102,101,17] are practically useful.…”
Section: Related Workmentioning
confidence: 99%
“…, G p of the edges of the embedded graph G in the proof of Theo- Floorplanning is a fundamental issue in circuit layout [106,43,69,62,51,108,32,8,17,58,24,57,91,68,84,4]. Motivated by VLSI physical design, various representations of floorplans were proposed [110,109,33]. Designing a floorplan to meet a certain criterion is NP-complete in general [87,44,100], so heuristic techniques such as simulated annealing [102,101,17] are practically useful.…”
Section: Related Workmentioning
confidence: 99%
“…FT Squeeze [5] FT Squeeze can represent any rec-dissection of n rooms by a permutation II of size TI [5], and can be decoded in O(n) time [6], [7].…”
Section: Rectangular Dissectionmentioning
confidence: 99%
“…In a few years, 2.5-dimensional FT Squeeze [8], which is ob tained by expanding FT Squeeze [5] and represents stacked-recdissection with a permutation and a sequence, was proposed.…”
Section: Introductionmentioning
confidence: 99%
“…For application in VLSI physical design, several encodings of rectangular drawings have been published: For example, H-Sequence [2], EQ-Sequence [3], FT-Squeeze [5], and so on. The bit length of codes is a mesure of encoding schemes [4].…”
Section: Introductionmentioning
confidence: 99%