A survey and comparison of digital logic simulators

Abstract

In this paper, we present a comprehensive survey of digital logic simulators from the past twenty years to present. First, we summarize the digital logic simulation characteristics. Next, we analyze a comprehensive set of simulators for their timing model, simulation mode, logic values, and fault simulation capabilities. I. LOGIC SIMULATION CHARACTERISTICSSeveral fundamental issues describe the functionality and flexibility of a digital logic circuit simulator. Primary among these considerations is the implementation of the basic simulation mechanism. There are two basic methods for digital logic simulation, compiled and event-driven simulations [23]. A. Compiled simulationA compiled simulator converts the circuit netlist into a sequence of machine language instructions that reflect the functions and interconnections of every element in the circuit. A circuit value table contains an entry that stores the current value of each logic element or net. The instructions obtain input values from this table and store results back into the table. Output values are computed using machine language instructions that reflect the function of the element. Compiled simulation is mainly oriented toward functional verification particularly since it is not concerned with the timing of the circuit. Since compiled simulators do not provide the accurate timing estimates, we will focus on event-driven simulators in the remainder of this paper. B. Event-driven simulationAn event-driven simulator can be implemented to operate on a set of tables that model the circuit. For each circuit node (net), the table has an entry of the logic state and the strength of the source or sources driving the node. An event is said to have occurred when a signal changes state on an input or the output of a circuit element, and is stored in an event queue to be scheduled. The simulator keeps track of the current time and the event queue that holds future events. An evaluation list keeps track of circuit elements whose inputs have changed. The evaluation list is processed after the event queue is processed for that time point. This chain of eventqueue processing followed by the evaluation-list processing is a simulation cycle.One efficient method to increase simulator performance is that of selective trace which greatly reduces the number of events to be triggered. It is based on the fact that some of the events may not alter the output of an element, so fan-out of this element is unaltered by the excitation that caused the evaluation. Thus, when an element's output does not change after computing with updated inputs, following its fan-out is unnecessary. C.Timing model The circuits being modeled rely both on correct logical operation of the components in the circuit and on correct relative timing of signals passing through the circuit. In an event-driven simulation, wires are usually assumed to be without any delay and logic elements are typically assumed to have lumped delay. The timing model of a simulator can vary from zero delay to min/max delay. A zero...