A Survey of Low Power Design Techniques for Last Level Caches

Ofori-Attah, Emmanuel; Wang, Xiaohang; Agyeman, Michael Opoku

doi:10.1007/978-3-319-78890-6_18

Cited by 3 publications

(1 citation statement)

References 42 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On-chip cache memories account for a significant portion [70][71][72][73][74][75][76][77] of power consumption in embedded devices. Therefore, for mobile devices that run on batteries, efficient power optimization techniques are highly in demand as the sizes of transistors progressively decreases.…”

Section: Reducing Power Consumption In the Cache Architecturementioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

Self Cite

View full text Add to dashboard Cite

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

show abstract

Section: Reducing Power Consumption In the Cache Architecturementioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

Self Cite

View full text Add to dashboard Cite

show abstract

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Ofori-Attah

Agyeman

2023

IEEE Access

View full text Add to dashboard Cite

Increase in chip inactivity in the future threatens the performance of many-core systems and therefore, efficient techniques are required for continuous scaling of transistors. As of a result of this challenge, future proposed many-core system designs must consider the possibility of a 50% functioning chip per time as well maintaining performance. Fortunately, this 50% inactivity can be increased by managing the temperature of active nodes and the placement of the dark nodes to leverage a balance working chip whilst considering the lifetime of nodes. However, allocating dark nodes inefficiently can increase the temperature of the chip and increase the waiting time of applications. Consequently, due to stochastic application characteristics, a dynamic rescheduling technique is more desirable compared to fixed design mapping. In this paper, we propose an Ageing Before Temperature Electromigration-Aware, Negative Bias Temperature Instability (NBTI) & Time-dependent Dielectric Breakdown (TDDB) Neighbour Allocation (ABENA 2.0), a dynamic rescheduling management system which considers the ageing and temperature before mapping applications. ABENA also considers the location of active and dark nodes and migrate task based on the characteristics of the nodes. Our proposed algorithm employ Dynamic Voltage Frequency Scaling (DVFS) to reduce the Voltage and Frequency (VF) of the nodes. Results show that, our proposed methods improve the ageing of nodes compared to a conventional round-robin management system by 10% in temperature, and 10% ageing.

show abstract

ABENA: An Ageing before Temperature Electromigration-Aware Neighbour Allocation for Many-Core Architectures

Ofori-Attah

Agyeman

2021

2021 4th International Conference on Data Storage and Data Engineering

View full text Add to dashboard Cite

The percentage of inactive nodes or dark nodes (we refer to dark nodes as dumso) in many-core systems increases because of power dissipation caused by continuous scaling in technology. To address this challenge, existing work employ several techniques. Some techniques place the dumso nodes strategically between active nodes to alleviate the temperature by choosing the nodes which are far away from each other. However, this increases the latency between nodes which require inter communication leading to performance degradation. Others employ Dynamic Thermal Management (DTM) to vary the Voltage Frequency (V/F) Scaling of the nodes whilst Task migration is used to migrate tasks. In this paper, an Ageing Before Temperature Eletromigration-Aware Neighbour Allocation (ABENA) is proposed to alleviate the temperature of the nodes by using the Lifetime of nodes as the main parameter. Experiments show that our approach improves the lifetime of nodes.

show abstract

A Survey of Low Power Design Techniques for Last Level Caches

Cited by 3 publications

References 42 publications

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

ABENA: An Ageing before Temperature Electromigration-Aware Neighbour Allocation for Many-Core Architectures

Contact Info

Product

Resources

About