A survey of multicore processors

Blake, Geoffrey; Dreslinski, Ronald G.; Mudge, Trevor

doi:10.1109/msp.2009.934110

Cited by 228 publications

(110 citation statements)

References 4 publications

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“…We benchmark our implementations on both an Intel Atom N270 with 1.6 GHz and a Core i7 with 3.3 GHz (see [15] for more details on multicore platforms), compiled with the Intel C compiler icc 11. We plot the throughput versus the data rate; i.e., if we measure a time of t micro seconds to receive 25 OFDM symbols then the throughput is (25NDBPS)/t bit/s and the data rate is NDBPS/TSYM.…”

Section: Resultsmentioning

confidence: 99%

Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore

Berger

Arbatov

Voronenko

et al. 2011

2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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We present a software-only implementation of an IEEE 802.11a (WiFi) receiver optimized for Intel multicore platforms. The receiver is about 50 times faster than a straightforward C implementation, i.e., an implementation that has the same functionality, but leaves optimization completely to the compiler. Our hand-optimized implementation achieves real-time for all data rates up to the maximum of 54 Mbit/s on a Core i7, clocked at 3.3 GHz, and for up to 12 Mbit/s on an Atom, clocked at 1.6 GHz, using two cores in both cases. To achieve this performance we use up to two threads, up to 16-way vectorization using Intel's SSE, and various other optimizations.

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Section: Resultsmentioning

confidence: 99%

Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore

Berger

Arbatov

Voronenko

et al. 2011

2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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“…In the homogeneous architecture, all the cores are identical, and they break up the overall computations and run them in parallel to improve overall performance of the processor [6]. The heterogenous cores have more than one type of cores, they are not identical, each core can handle different application.…”

Section: Introductionmentioning

confidence: 99%

“…The power problem is very important, while performance still desired as predictions from the ITRS Roadmap [7] predicting a need for 300x more performance by 2022 with a chip with 100x more cores than current one [8] as shown in Figure 1. Power = Voltage 2 * frequency (2) The multicore processor designer should balance between power (which related to the voltage and frequency) and instructions per ASTESJ ISSN: 2415-6698 cycle (IPC, which is related to the speed and throughput) when developing processors to get a high performance and power efficiency of the processor.…”

Section: Introductionmentioning

confidence: 99%

“…Power = Voltage 2 * frequency (2) The multicore processor designer should balance between power (which related to the voltage and frequency) and instructions per ASTESJ ISSN: 2415-6698 cycle (IPC, which is related to the speed and throughput) when developing processors to get a high performance and power efficiency of the processor. (DPE) and overall performance [7,8].…”

Section: Introductionmentioning

confidence: 99%

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A Survey on Parallel Multicore Computing: Performance & Improvement

Surakhi¹,

Khanafseh²,

Sarhan³

2018

Adv. sci. technol. eng. syst. j.

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“…To delivery more efficient computing power, we depend more and more on advantages of parallel processing [1], [2]. Multi-core processors become the first choice of parallel processing platforms [3].…”

Section: Introductionmentioning

confidence: 99%

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

Zhang

Wang

Sheng

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYCache affinity has been proved to have great impact on the performance of packet processing applications on multi-core platforms. Flow-based packet scheduling can make the best of data cache affinity with flow associated data and context structures. However, little work on packet scheduling algorithms has been conducted when it comes to instruction cache (I-Cache) affinity in modified pipelining (MPL) architecture for multi-core systems. In this paper, we propose a protocol-aware packet scheduling (PAPS) algorithm aiming at maximizing I-Cache affinity at protocol dependent stages in MPL architecture for multi-protocol processing (MPP) scenario. The characteristics of applications in MPL are analyzed and a mapping model is introduced to illustrate the procedure of MPP. Besides, a stage processing time model for MPL is presented based on the analysis of multi-core cache hierarchy. PAPS is a kind of flowbased packet scheduling algorithm and it schedules flows in consideration of both application-level protocol of flows and load balancing. Experiments demonstrate that PAPS outperforms the Round Robin algorithm and the HRW-based (HRW) algorithm for MPP applications. In particular, PAPS can eliminate all I-Cache misses at protocol dependent stage and reduce the average CPU cycle consumption per packet by more than 10% in comparison with HRW.

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A survey of multicore processors

Cited by 228 publications

References 4 publications

Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore

Real-time software implementation of an IEEE 802.11a baseband receiver on Intel multicore

A Survey on Parallel Multicore Computing: Performance & Improvement

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

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