A survey of on-chip monitors

Rahimipour, Somayeh; Flayyih, Wameedh Nazar; El-Azhary, Ismail; Shafie, Suhaidi; Rokhani, Fakhrul Zaman

doi:10.1109/iccircuitsandsystems.2012.6408286

Cited by 5 publications

(4 citation statements)

References 31 publications

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“…In this paper, the proposed V/F tuning algorithm uses the delay information produced by the critical-path timing monitor circuits such as CPM [8]. Several studies have shown that CPM can effectively provide timing margin information at every clock cycle for speedy response with only a slight increase in design complexity and area [9][10][11][12].…”

Section: Tunable Ntc Architecturementioning

confidence: 99%

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li¹,

Kim²,

Heo³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage-and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiplevoltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

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Section: Tunable Ntc Architecturementioning

confidence: 99%

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li¹,

Kim²,

Heo³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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“…This technique of supply current monitoring, known as IDDQ testing, has been adopted by many in the semiconductor industry [2,11,12,13,14]. In fact, as electronic designs continue to grow in complexity, there is interest in having multiple monitoring blocks that track changes in temperature, voltage, and error data [15]. Another idea that motivated the development of the proposed current monitoring technique is the transmission of data over the power-line, referred to as Power-Line Communications (PLC) in the literature [16,17,18].…”

Section: Motivationmentioning

confidence: 99%

“…Figure 5-15 Table 5.1 below shows a summary of the chosen component values. 160 Ω R 35 160 Ω R 14 10 kΩ R 36 160 Ω R 15 10 kΩ R 37 10 kΩ R 16 5.1 kΩ C 1 10 µF R 17 160 Ω C 2 10 µF R 18 10 kΩ C 3 0.1µF R 19 10 kΩ C 4 0.1 µF R 20 160 Ω C ---C:\Users\Anas\Dropbox\6_132_files\6_132_files\Bandgap and references\spice\bandgap.raw ---…”

Section: -5 V and 12 V Referencesmentioning

confidence: 99%

Power Monitoring In Integrated Circuits

Bastami

2014

Qatar Foundation Annual Research Conference Proceedings Volume 2014 Issue 1

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Power monitoring is needed in most electrical systems, and is crucial for ensuring reliability in everything from industrial and telecom applications, to automotive and consumer electronics. Power monitoring of integrated circuits (ICs) is also essential, as today ICs exist in most electrical and electronic systems, in a vast range of applications. Many ICs, including power ICs, have functional blocks across the chip that are used for different purposes. Measuring circuit block currents in both analog and digital ICs is important in a wide range of applications, including power management as well as IC testing and fault detection and analysis. For example, the presence of different kinds of faults in IC circuit blocks during IC fabrication causes the currents flowing through these circuit blocks to change from the expected values. There has been general interest in monitoring currents through different circuit blocks in an attempt to identify the location and type of the faults. Previous works on nonintrusive load monitoring as well as on power-line communications (PLCs) provide motivation for the work presented here. The techniques are extended and used to develop a new method for power monitoring in ICs. Most solutions to the challenge of measuring currents in different circuit blocks of the IC involve adding circuitry that is both costly and power consuming. In this work, a new method is proposed to enable individual measurement of current consumed in each circuit block within an IC while adding negligible area and power overhead. This method works by encoding the individual current signatures in the main supply current of the IC, which can then be sensed and sampled off-chip, and then disaggregated through signal processing. A demonstration of this power monitoring scheme is given on a modular discrete platform that is implemented based on the UC3842 current-mode controller IC, which can also be used for educational purposes.

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“…The temporal DTMs perform cooling by slowing down the switching activities of the overheated nodes, or by shutting down some functions of 3-D NoC [12]. Some efficient techniques, such as dynamic voltage scaling [13], dynamic frequency scaling (DFS) [14], dynamic voltage and frequency scaling [15], and clock throttling [16], are widely applied to DTMs.…”

mentioning

confidence: 99%

DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures

Zheng

Zhou

et al. 2016

IEEE Trans. VLSI Syst.

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Three-dimensional network-on-chip (NoC)-bus hybrid architectures are motivated to achieve lower propagation latency and higher bandwidth in vertical direction, by taking the advantage of the short interwafer distances in 3-D integrated circuits. However, 3-D integration technology increases the power density of the chip, and thus, results in thermalrelated problems. Therefore, to ensure that the chip operates within the safe temperature range, while keeping the traffic performance undegraded, this paper proposes a proactive thermal management scheme based on dynamic frequency scaling bus (DFSB) for developing thermal-aware 3-D NoC-bus architectures. The novel solution includes thermal-aware frequency scaling policy (TFSP) and frequency-aware adaptive routing (FAAR), for the temporal and spatial management separately. TFSP dynamically and proactively adjusts the frequency of DFSB, according to the predicted thermal variation, to throttle the data flow for heat dissipation. Meanwhile, FAAR cooperated with TFSP by migrating the data flow to balance the distribution of traffic and thermal, and thus, unacceptable local data congestion and latency are avoided. In order to show the effectiveness of the proposed solution, we compare it against global throttling and downward routing thermal management solutions in a 4 × 4 × 4 3-D NoC-bus architecture. Experimental results show that, under the thermal limitation of 378.15 K, our proposed solution outperforms the other two solutions by 24% and 56.2% improvement in throughput, and 33.1% and 45.7% reduction in latency.Index Terms-3-D integration, adaptive routing, dynamic frequency scaling (DFS), network-on-chip (NoC)-bus hybrid architecture, thermal management.

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A survey of on-chip monitors

Cited by 5 publications

References 31 publications

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Power Monitoring In Integrated Circuits

DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures

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