A survey of recent contributions on low power NoC architectures

Ofori-Attah, Emmanuel; Agyeman, Michael Opoku

doi:10.1109/sai.2017.8252226

Cited by 13 publications

(3 citation statements)

References 26 publications

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“…To overcome these challenges, several design aspects have been proposed in literature [9]- [13], [13], [14]. One design aspect which can be exploited in different ways is architectural heterogeneity: whether this being the implementation of different sizes of resources as depicted in [15] or incorporating CPU/GPU [16], [17].…”

Section: Introductionmentioning

confidence: 99%

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Ofori-Attah

Agyeman

2023

IEEE Access

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Increase in chip inactivity in the future threatens the performance of many-core systems and therefore, efficient techniques are required for continuous scaling of transistors. As of a result of this challenge, future proposed many-core system designs must consider the possibility of a 50% functioning chip per time as well maintaining performance. Fortunately, this 50% inactivity can be increased by managing the temperature of active nodes and the placement of the dark nodes to leverage a balance working chip whilst considering the lifetime of nodes. However, allocating dark nodes inefficiently can increase the temperature of the chip and increase the waiting time of applications. Consequently, due to stochastic application characteristics, a dynamic rescheduling technique is more desirable compared to fixed design mapping. In this paper, we propose an Ageing Before Temperature Electromigration-Aware, Negative Bias Temperature Instability (NBTI) & Time-dependent Dielectric Breakdown (TDDB) Neighbour Allocation (ABENA 2.0), a dynamic rescheduling management system which considers the ageing and temperature before mapping applications. ABENA also considers the location of active and dark nodes and migrate task based on the characteristics of the nodes. Our proposed algorithm employ Dynamic Voltage Frequency Scaling (DVFS) to reduce the Voltage and Frequency (VF) of the nodes. Results show that, our proposed methods improve the ageing of nodes compared to a conventional round-robin management system by 10% in temperature, and 10% ageing.

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Section: Introductionmentioning

confidence: 99%

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Ofori-Attah

Agyeman

2023

IEEE Access

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“…Most conventional NoCs adopt a buffered architecture, but deadlocks and the inability to handle adversarial traffic patterns are well-known problems in buffered NoCs [7]. A buffered NoC has another major drawback: buffers consume a large amount of power and silicon real estate [8][9][10][11]. [8] showed that removing buffers in its proposed architecture could lower power consumption by 40% and reduce silicon area by 70%.…”

Section: Introductionmentioning

confidence: 99%

Designing Nonblocking Networks With a General Topology

Lin¹,

Lea

2022

IEEE Access

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Conventional theory for designing strictly nonblocking networks, such as crossbars or Clos networks, assumes that these networks have a centralized topology. Many new applications, however, require networks to have a distributed topology, like 2-D mesh or torus. In this paper, we present a new theoretical framework for designing such nonblocking networks. The framework is based on a linear programming formulation originally proposed for solving the hose-model traffic routing problem. The main difference, however, is that the link bandwidths in our problem must be discrete. This makes the problem much more challenging. We show how to apply the developed theorems to tackle the problem of designing bufferless NoCs (networks-on-chip). The proposed bufferless NoCs are deadlock/livelock-free and consume significantly less power than their buffered counterparts. We also present a multi-slice technique to reduce node capacity variations. This can make the proposed NoC architecture more cost efficient in a VLSI (very large-scale integration) implementation. In addition, we offer a detailed delay/throughput performance evaluation of the proposed bufferless NoC in the paper. INDEX TERMSNonblocking networks, Networks-on-chip (NoCs), Bufferless, Hose model.

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“…A large part of the existing literature on NoC design [3,7,21] has been devoted to the improvement of router architecture and routing algorithms. While NoC topologies are often assumed regular in these studies, here we rather consider both regular and irregular topologies for optimizing the NoC performances, e.g.…”

Section: Introductionmentioning

confidence: 99%

GANNoC: A Framework for Automatic Generation of NoC Topologies using Generative Adversarial Networks

Mirka

Sassatelli

Gamatié

2021

Proceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools Proceeding

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We propose GANNoC, a framework for automatic generation of customized Network-on-Chip (NoC) topologies, which exploits generative adversarial networks (GANs) learning capabilities. We define the problem of NoC generation as a graph generation problem, and train a GAN to produce such graphs. We further present a Reward-WGAN (RWGAN) architecture, based on the Wasserstein GAN (WGAN). It is coupled to a reward network enabling to steer the resulting generative system towards topologies having desired properties. We illustrate this capability through a case study aimed at producing topologies with a specific number of physical connections. After training, the generative network produces unique topologies with a 36% improvement regarding the number of connections, when compared to those found in the training dataset. NoCs' performance assessment is carried out using the Ratatoskr 3D-NoC simulator with state-of-the-art characteristics. Results suggest interesting opportunities in learning correlations between intrinsic NoC features and resulting performance.

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A survey of recent contributions on low power NoC architectures

Cited by 13 publications

References 26 publications

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Designing Nonblocking Networks With a General Topology

GANNoC: A Framework for Automatic Generation of NoC Topologies using Generative Adversarial Networks

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