A Survey of Security Attacks on Silicon Based Weak PUF Architectures

Yehoshuva, Chintala; Adhithan, R. Raja; Anandakumar, N. Nalla

doi:10.1007/978-981-16-0422-5_8

Cited by 6 publications

(2 citation statements)

References 39 publications

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“…Silicon-based PUF take advantages of small and random variations within materials, which cause circuits to response slightly different to the same excitation at electrical and physical level [46]. Signals may propagate at different speeds through the material, or thresholds voltages may change.…”

Section: Physical Unclonable Functions Modelingmentioning

confidence: 99%

Predictor-corrector models for lightweight massive machine-type communications in Industry 4.0

Bordel

Alcarria

Chung

et al. 2023

ICA

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Future Industry 4.0 scenarios are characterized by seamless integration between computational and physical processes. To achieve this objective, dense platforms made of small sensing nodes and other resource constraint devices are ubiquitously deployed. All these devices have a limited number of computational resources, just enough to perform the simple operation they are in charge of. The remaining operations are delegated to powerful gateways that manage sensing nodes, but resources are never unlimited, and as more and more devices are deployed on Industry 4.0 platforms, gateways present more problems to handle massive machine-type communications. Although the problems are diverse, those related to security are especially critical. To enable sensing nodes to establish secure communications, several semiconductor companies are currently promoting a new generation of devices based on Physical Unclonable Functions, whose usage grows every year in many real industrial scenarios. Those hardware devices do not consume any computational resource but force the gateway to keep large key-value catalogues for each individual node. In this context, memory usage is not scalable and processing delays increase exponentially with each new node on the platform. In this paper, we address this challenge through predictor-corrector models, representing the key-value catalogues. Models are mathematically complex, but we argue that they consume less computational resources than current approaches. The lightweight models are based on complex functions managed as Laurent series, cubic spline interpolations, and Boolean functions also developed as series. Unknown parameters in these models are predicted, and eventually corrected to calculate the output value for each given key. The initial parameters are based on the Kane Yee formula. An experimental analysis and a performance evaluation are provided in the experimental section, showing that the proposed approach causes a significant reduction in the resource consumption.

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Section: Physical Unclonable Functions Modelingmentioning

confidence: 99%

Predictor-corrector models for lightweight massive machine-type communications in Industry 4.0

Bordel

Alcarria

Chung

et al. 2023

ICA

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“…A limited response space could be the result of challenges. The outside world might have access to any or all of the responses produced by weak PUFs [38,39]. This may be a trait of some implementations which could in some circumstances compromise their security.…”

Section: Based On Securitymentioning

confidence: 99%

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Lata,

Cenkeramaddi

2023

Cryptography

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Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.

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