A Survey of the Heterogeneous Computing Platform and Related Technologies

Liu, Fei; Liang, Yi; Wang, Ling-ze

doi:10.12783/dtetr/imeia2016/9229

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…There, the application is portioned in a way that tasks are distributed among coprocessors depending on their specialized processing capabilities. Currently, the most common heterogeneous systems are made of a multicore Central Processing Unit (CPU) and GPU [5]. Serial portions of applications are run on the former, while data-parallel, compute-intensive portions are offloaded to the latter.…”

Section: Introductionmentioning

confidence: 99%

Performance engineering for HEVC transform and quantization kernel on GPUs

et al. 2020

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Continuous growth of video traffic and video services, especially in the field of high resolution and high-quality video content, places heavy demands on video coding and its implementations. High Efficiency Video Coding (HEVC) standard doubles the compression efficiency of its predecessor H.264/AVC at the cost of high computational complexity. To address those computing issues high-performance video processing takes advantage of heterogeneous multiprocessor platforms. In this paper, we present a highly performance-optimized HEVC transform and quantization kernel with all-zero-block (AZB) identification designed for execution on a Graphics Processor Unit (GPU). Performance optimization strategy involved all three aspects of parallel design, exposing as much of the application's intrinsic parallelism as possible, exploitation of high throughput memory and efficient instruction usage. It combines efficient mapping of transform blocks to thread-blocks and efficient vectorized access patterns to shared memory for all transform sizes supported in the standard. Two different GPUs of the same architecture were used to evaluate proposed implementation. Achieved processing times are 6.03 and 23.94 ms for DCI 4K and 8K Full Format, respectively. Speedup factors compared to CPU, cuBLAS and AVX2 implementations are up to 80, 19 and 4 times respectively. Proposed implementation outperforms previous work 1.22 times.

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Section: Introductionmentioning

confidence: 99%

Performance engineering for HEVC transform and quantization kernel on GPUs

et al. 2020

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Optimizing resource utilization for large scale problems through architecture aware scheduling

Elsawwaf,

Aly,

Faheem

et al. 2024

Sci Rep

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Rapid development realms of parallel architectures and its heterogeneity have inspired researchers to invent new scheduling strategies to efficiently distribute workloads among these architectures in a way that may lead to better performance. This paper presents a comprehensive study on optimizing resource utilization for large-scale problems by employing architecture-aware scheduling techniques. We conducted a series of experiments to measure the execution times of various architectures with different problem sizes. These experiments have been conducted multiple times to minimize measurement variance. The findings from these experiments are utilized to develop a scheduling strategy that enables faster completion of larger data-parallel problems while maximizing resource utilization. The proposed approach makes performance enhancement with 16.7% for large data size. It has a significant impact on enhancing computational efficiency and reducing costs in high-performance computing environments.

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A Survey of the Heterogeneous Computing Platform and Related Technologies

Cited by 2 publications

References 15 publications

Performance engineering for HEVC transform and quantization kernel on GPUs

Performance engineering for HEVC transform and quantization kernel on GPUs

Optimizing resource utilization for large scale problems through architecture aware scheduling

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