A survey on energy-efficient methodologies and architectures of network-on-chip

Abbas, Abdulla; Ali, Mazhar; Fayyaz, Ahmad; Ghosh, Anupam; Kalra, Anshul; Khan, Samee U.; Khan, Muhammad Usman Shahid; Menezes, Thiago D. S. De; Pattanayak, Sayantica; Sanyal, Alarka; Usman, Saeeda

doi:10.1016/j.compeleceng.2014.07.012

Cited by 43 publications

(18 citation statements)

References 38 publications

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“…When the polling sequence is changed, the ONUs will allocate longer idle times which will activate to sleep longer time as well. It was noticed from the literature survey that the polling sequence arrangement affect the energy efficiency of the network [1], [2], [19][20][21][22][23][24]. To achieve energy efficiency under a low-load network, the LASA was jointly working with the fixed minimal transmission time (FMT) and this was called as the LASA-FMT scheme.…”

Section: Load Adaptive Sequence Arrangement (Lasa) With Fixed Minimalmentioning

confidence: 99%

“…FAMF ensures entries are purely based on the network i.e total lists of entries maintained by core nodes are restricted to possible routes available in the network. The entries in the table has to be lesser than that of entries served by the router [18][19][20]. The FAMF Model is considered as complex one as compared to FAMTAR.…”

Section: Flow Aggregation Mechanism For Famtarmentioning

confidence: 99%

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FA-LAR: an efficient flow aware based load adaptive routing scheme for optical communication networks

Swaminathan

Sakthivel

Subasree

2018

IJET

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Routing Protocols have been proposed to enable the network to identify and suggest various routes to number of demanded flows. In the Flow-Aware Network Models, the routes are identified and selected with the help of Flow Tables or Flow Identifiers that proposed by Flow Aggregation Mechanism. That is, users can define a Flow Aggregation Model to suggest routes depend on their defined-demanded flows and this model effectively handles many flows, which helps core routers to profit aggregate routing. This is an efficient and effective approach to identify a best route to achieve required performance. It is noted from the literature survey that the Flow-Aware Multi-Topology Adaptive Routing (FAMTAR) was proposed for achieving higher Network performance through multipath solutions. This FAMTAR Model was implemented and studied thoroughly. From the experimental results, it was noticed that this model unable to i. detect and manage bulk flow, ii. Control Traffic Loss and iii. Maintain Deviation of Links Load against Traffic Load. To address the above mentioned issues, this research work is proposed an efficient Flow-Aware based Load Adaptive Routing (FA-LAR). This model is developed and implemented in ns3 and the simulation results are analysed carefully. From the experimental results, it is noticed that the prosed Model, FA-LAR is performing well as compared with the existing FAMTAR in terms of Queueing Delay, Throughput, Power Consumption (Energy Dissipation), and Load Deviation. It is also noticed that the proposed model unable to achieve higher Throughput for Low Load.

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Section: Load Adaptive Sequence Arrangement (Lasa) With Fixed Minimalmentioning

confidence: 99%

Section: Flow Aggregation Mechanism For Famtarmentioning

confidence: 99%

FA-LAR: an efficient flow aware based load adaptive routing scheme for optical communication networks

Swaminathan

Sakthivel

Subasree

2018

IJET

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“…Networks-on-Chip (NoCs) have emerged as the key onchip communication architecture for multiprocessor systemson-chip and chip multiprocessors [1] [27] [29]. Achieving scaling performance for future many-core systems will require high-performance, yet energy-efficient on-chip interconnection networks [2] [27] [28].…”

Section: Introductionmentioning

confidence: 99%

Circuit design of Clos-based on-chip interconnection networks

Jiang

Yang

2016

Microprocessors and Microsystems

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Single-hop non-blocking networks have the advantage of providing uniform latency and throughput, which is important for cache-coherent network-on-chip systems. This paper focuses on high performance circuit designs of multi-stage non-blocking networks as alternatives to crossbars. Existing work shows that Benes networks have much lower transistor count and smaller circuit area but longer delay than crossbars. To reduce the timing delay, we propose to design the Clos network built with larger size switches. Using less than half number of stages than the Benes network, the Clos network with 4x4 switches can significantly reduce the timing delay. The circuit designs of both Benes and Clos networks in different sizes are conducted considering two types of implementation of the configurable switch: with NMOS transistors only and full transmission gates (TGs). The layout and simulation results under 45nm technology show that the TG-based implementation demonstrates much better signal integrity than its counterpart. Clos networks achieve average 60% lower timing delay than Benes networks with even smaller area and power consumption.

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“…Currently, such flexibility can be provided by a large packet-switched NoC with an over-engineered total bandwidth. Unfortunately, such a NoC would result in a significant area overhead because only a fraction of its bandwidth is really utilized for a given application ( [17,30,31]). Another way is the reconfigurable NoC that enhanced the dynamical reconfigurability of the SoC platform; therefore, this also results in the further reduction in area and power consumption of the design ( [17,30]).…”

Section: Evolution Of System-on-chipsmentioning

confidence: 99%

“…[9,10] and [11]), fault tolerance design (e.g. [12,13] and [14]), design methodologies ( [15,16] and [17]), operation systems, 1859-378X-2017-34. .…”

Section: Introductionmentioning

confidence: 99%

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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A survey on energy-efficient methodologies and architectures of network-on-chip

Cited by 43 publications

References 38 publications

FA-LAR: an efficient flow aware based load adaptive routing scheme for optical communication networks

FA-LAR: an efficient flow aware based load adaptive routing scheme for optical communication networks

Circuit design of Clos-based on-chip interconnection networks

A Survey on Reconfigurable System-on-Chips

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