A survey on system level energy optimisation for MPSoCs in IoT and consumer electronics

Ali, Haider; Tariq, Umair Ullah; Hardy, Jennifer; Zhai, Xiaojun; Liu, Lu; Zheng, Yongjun; Bensaali, Fayçal; Amira, Abbes; Fatema, Kaniz; Antonopoulos, Nick

doi:10.1016/j.cosrev.2021.100416

Cited by 25 publications

(11 citation statements)

References 119 publications

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“…Internet-of-Things (IoT) environment was recently built upon Multiprocessors System-on-Chip (MPSoCs) platforms ultimately [10]. The MPSoCs have become a legitimate platform for computing and may be used in various computationally intensive real-time applications.…”

Section: E Significance and Implications 1) Mpsoc Role In Iotmentioning

confidence: 99%

“…Wang et al [14] employed the CRITIC technique to provide a trust evaluation method for service composition in cloud manufacturing. Gaur et al [10] presented a stakeholder assessment based on the qualities that stakeholders possessed, mainly relying on the evaluation of attribute weights utilizing the CRITIC technique to resolve any potential link between the attributes in estimating their weight. Khargotra et al [15] analyzed the effectiveness of delta-shaped barriers in a solar water heating system using CRITIC.…”

Section: Studies On Criticmentioning

confidence: 99%

“…The output of both alternatives and criteria given by 𝑫𝑴[𝒅 𝒊𝒋 ], with both 𝒊 𝒕𝒉 𝐚𝐧𝐝 𝒋 𝒕𝒉 respectively. See Equation (10).…”

Section: B Phase 2: Criteria Weightingmentioning

confidence: 99%

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Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

et al. 2023

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Context: Denial-of-Service Attack countermeasure techniques (DoS A-CTs) evaluation is a multi-criteria decision-making (MCDM) problem based on different MPSoCs of IoT platform design, performance, and design overhead. Therefore, the Fermatean by fuzzy decision opinion score method (F-FDOSM) for prioritizing the powerful countermeasure technique against Denial-of-Service (DoS) attack is the best approach because it employs the most efficient MCDM ranking technique. Nonetheless, the FDOSM method needs to weigh the criteria before being submitted for the ranking process. In order to address this theoretical challenge, the Criteria-importance through inter-criteria correlation (CRITIC) technique can be applied as an effective MCDM weighting technique to offer an explicit weight for a set of criteria with no inconsistency based on the standard deviation, which uses correlation analysis to determine the relevance of each criterion. Objectives: This research proposes a Fermatean-FDOSM framework for evaluating DoS A-CTs in the context of MPSoCs-based IoT and CRITIC techniques to weight the criteria. Methods: The methodology is presented in three phases. Firstly, a proposed countermeasure techniques dataset was collected that included eighteen defense approaches (e.g., Sniffer, SeRA, and RLAN) based on thirteen criteria (e.g., size, power, latency, and effectiveness ... etc.). Then, the decision matrix was built based on an intersection of the countermeasure techniques as an alternative and MPSoC design and performance criteria. Then, the multi-criteria decision-making methods were integrated. The CRITIC method for criteria weighting was followed by the development of the Fermatean-FDOSM method for ranking. Results: (1) CRITIC weighting shows that MPSoC NoC Routing Algorithm (XY and YX) is the highest weight criterion, whereas latency (clock/cycle) is the less weight criterion. ( 2) The Fermatean-FDOSM-based group ranking shows that the Collision Point Router Detection (CPRD) countermeasure technique is the first-ranked alternative compared to the Secure Model Checkers (SMCs) approach. (3) The DoS A-CTs priority ranks were subjected to a systematic ranking that was confirmed by solid correlation results throughout thirteen criterion weight values. A comparison with recent studies confirmed the feasibility of the proposed framework. Conclusion: The results of this research are expected to provide a specific understanding and guide for those who want to engage in MPSoCs-based IoT and NoC communication security research with decision theory.

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Section: E Significance and Implications 1) Mpsoc Role In Iotmentioning

confidence: 99%

Section: Studies On Criticmentioning

confidence: 99%

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Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

et al. 2023

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“…Multicore architectures integrate multiple processors on a single chip, leading to platforms with low supply frequency, high data throughput and better energy efficiency [1]. With the development of nanoscale technologies, various processors communicate via the Network-on-Chips (NoC), instead of traditional, non-scalable, data buses [2].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFS

Zhou

Kritikakou

et al. 2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Task deployment plays an important role in the overall system performance, especially for complex architectures, including several cores with Dynamic Voltage and Frequency Scaling (DVFS) and Network-on-Chips (NoC). Task deployment affects not only the energy consumption but also the real-time response and reliability of the system. In this work, a task deployment approach is proposed to optimize the overall system energy consumption, including computation of the cores and communication of the NoC, under task reliability and real-time constraints. More precisely, the task deployment approach combines task allocation and scheduling, frequency assignment, task duplication, and multipath data routing. The task deployment problem is formulated using mixed-integer non-linear programming. To find the optimal solution, the original problem is equivalently transformed to mixed-integer linear programming, and solved by state-of-theart solvers. Furthermore, a decomposition-based heuristic, with low computational complexity, is proposed to deal with scalability. Finally, extended simulations evaluate the proposed methods.

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“…Some multiprocessor systems (MPS) are implemented directly using FPLDs (Ali et al, 2021). This is due to the fact that the reconfigurable hardware platform is fast enough, and most importantly, such multiprocessor systems become universal and flexibile in the process of computing a particular task (Reis & Fröhlich, 2020).…”

Section: Introductionmentioning

confidence: 99%

Experimental research of a shared memory subsystem with limited queue length for specialized reconfigurable multiprocessor systems

Martyshkin

Martens-Atyushev

2022

Ind. Jour. Manag. & Prod.

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Recently, reconfigurable systems based on field programmable logic devices (FPLDs) have been widely used in high-performance computing. The paper discusses issues related to the experimental research of a shared memory subsystem with a limited queue length of specialized reconfigurable multiprocessor systems using the developed mathematical modelling method. The paper presents the results of the method proposed by the authors for modelling multiprocessor systems based on open queuing networks with limited queue lengths. Based on these conditions, as well as the architectural features of the investigated processor-memory subsystem, expressions are calculated to estimate the exchange time and the resulting delays at each exchange stage. During the research, the main attention was paid to the dependence of the increase in the number of processor nodes in the processor-memory subsystem. As a result, the data obtained showed that the processor growth significantly affects the exchange time, creating a significant load on the common bus, as well as increasing delays at the stages when request transfer operation from the processor to the memory is performed. At the same time, the inadequate behaviour of experimental results and inaccuracy of their values when using the basic modelling method are explicitly tracked, which is reflected in the obtained graphs. Computational experiments were carried out to calculate the probabilistic-temporal characteristics of the "processor-memory" subsystem using the developed mathematical modelling methods. Based on the experimental results, it was determined that the delays occurring in subsystem's nodes and the time of exchange between the processor and memory modules depend on the query parameters and the processor-memory subsystem’s architectural characteristics.

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A survey on system level energy optimisation for MPSoCs in IoT and consumer electronics

Cited by 25 publications

References 119 publications

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFS

Experimental research of a shared memory subsystem with limited queue length for specialized reconfigurable multiprocessor systems

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