2020
DOI: 10.1007/s00034-020-01437-3
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A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique

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Cited by 9 publications
(13 citation statements)
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“…Where the charge injection is defned as the charge that exists between the source and drain terminals when the sample switch is turned of, and the clock feed through is defned as the charge injected due to the overlapping coupling capacitor between the gate and drain terminals. Consequently, it is preferable to implement the sample switch by using CMOS transmission gates [8,64,103] or the bootstrap switch in Figure 4 [2,5,6,11,17,22,24,31,34,45,53,58,63,65 Te variations in conductivity are reduced by utilizing the CMOS transmission gates, but the problem of input dependence still exists. Additionally, a large parasitic capacitor that limits the resolution of SAR appears.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
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“…Where the charge injection is defned as the charge that exists between the source and drain terminals when the sample switch is turned of, and the clock feed through is defned as the charge injected due to the overlapping coupling capacitor between the gate and drain terminals. Consequently, it is preferable to implement the sample switch by using CMOS transmission gates [8,64,103] or the bootstrap switch in Figure 4 [2,5,6,11,17,22,24,31,34,45,53,58,63,65 Te variations in conductivity are reduced by utilizing the CMOS transmission gates, but the problem of input dependence still exists. Additionally, a large parasitic capacitor that limits the resolution of SAR appears.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
“…In the SAR ADC for biomedical applications, the target design is to obtain power consumption of less than microwatts. So, the regular structure of the SAR sample and hold switch is the bootstrap circuit [63]. Te diferent circuit schemes are summarized in Table 1.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
“…The dynamic comparator has high input impedance, negligible static power consumption, rail-to-rail output swing, precise noise, and mismatch robustness, consequently, it's far pretty distinguished for SAR ADC in Ref. [1],Kasi Bandla, et.al, has reviewed that static power consumption is excessive in Dynamic Latch Comparator with Pre-Amplifier topology and consequently no longer most suitable for low power applications. However, the above-mentioned topology is ideal for correct evaluation the Charge Sharing Dynamic Latch Comparator (CSDLC) is used in order to have low energy.…”
Section: Literature Reviewmentioning
confidence: 99%
“…Hence, a power-efficient and fully programmable resolution ADC can substantially reduce the size and cost of the WBSN. In [7][8][9][10][11][12][13][14][15][16], adaptive-resolution ADC architectures are presented for implantable sensors. In all these papers, SAR ADC is designed with binary-weighted capacitive DAC using different switching methods.…”
Section: Introductionmentioning
confidence: 99%
“…The switched‐capacitor integrator SAR ADC [7] is implemented using operational transconductance amplifier (OTA) with programmable unity gain bandwidth (UGB) and slew rate, dynamic comparator, capacitors, switches and control logic. The advantages of switched‐capacitor integrator based SAR ADC over conventional SAR ADC are summarized as follows: the number of unit capacitors used in the binary‐weighted DAC is exponentially proportional to the resolution ( N bits).…”
Section: Introductionmentioning
confidence: 99%