A system-level solution to domino synthesis with 2 GHz application

Chappell, B.A.; Wang, X.; Patra, Priyadarsan; Saxena, Prashant; Vendrell, J.; Gupta, Sarthak; Varadarajan, Srenivas; Gomes, Wilfred; Hussain, Safina; Krishnamurthy, Harish K.; Venkateshmurthy, M.; Jain, Shailendra

doi:10.1109/iccd.2002.1106765

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…Shielding requirements for signal nets are generated by a timing/noise optimization engine according to signal nets' sensitivity and criticality. How to generate shield requirements for signal nets has been described in [3] and has been employed by [15] for modern micro-processor designs. Similar to [15], we assume the shielding requirements for nets are part of the input.…”

Section: Power Pitch and Signal Shielding Constraintsmentioning

confidence: 99%

See 1 more Smart Citation

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Lin

et al. 2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

137

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Section: Power Pitch and Signal Shielding Constraintsmentioning

confidence: 99%

“…If a valid track assignment solution can achieve this tighter low bound, then it must also have the minimum number of power nets. 3 The two edge power nets are counted as one in St because of the sharing between adjacent routing regions.…”

Section: Proofmentioning

confidence: 99%

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Lin

et al. 2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

137

View full text Add to dashboard Cite

show abstract

“…Shielding requirements for signal nets are generated by a timing/noise optimization engine according to signal nets' sensitivity and criticality. How to generate shield requirements has been described in [2] and has been employed by [10] for modern micro-processor designs. Similar to [10], we assume the shielding requirements for nets are part of the input.…”

Section: Preliminary and Design Constraintsmentioning

confidence: 99%

“…In this case, we cannot reduce any power net without violating the shielding constraints, therefore, the obtained number of power nets is minimum. Such a solution can be obtained by (1) alternating all m 2 s2-nets with power nets, and putting two s1-nets adjacent to the two outermost power nets; (2) sharing one power net between every remaining s1-net pair. As all s0-nets do not need any shields, the total power net number is the sum of the above two procedures:…”

Section: Power Net Estimationmentioning

confidence: 99%

Full-chip multilevel routing for power and signal integrity

Xiong¹,

Li²

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-micron designs. We present a novel design methodology that simultaneously considers global signal routing and power network design under integrity constraints. The key part to this approach is a simple yet accurate power net estimation formula that decides the minimum number of power nets needed to satisfy both power and signal integrity constraints prior to detailed layout. The proposed design methodology is a one-pass solution to the co-design of power and signal networks in the sense that no iteration between them is required in order to meet design closure. Experiment results using large industrial benchmarks show that compared to the state-of-the-art alternative design approach , the proposed method can reduce the power network area by 19.4% on average under the same signal and power integrity constraints with better routing quality , but use less runtime.

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Probabilistic congestion model considering shielding for crosstalk reduction

Xiong¹,

Li²

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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We extend an existing probabilistic congestion model to consider shielding for crosstalk reduction. We then develop a multilevel router to study the impact of various congestion models on routing congestion by using large industrial design examples. We show that (1) wlieri shielding is applied a s a post-routing optimization for crosstalk reduction, the existing probabilistic model, when conipared t o a deterministic routing-order dependent congestion model: reduces routing congestion by 17.1% on average under the given routing area constraints, or reduces routing area by 9.4% on average under thc given roiiting congestion constraints; ( 2 ) our extended prohahilistic congestion model considering shielding enaldes shieldirig reservation and minimization for routing and achieves routing congcstion (or area) reduction by 47.7% (or 31.U%) on average under the given routing area (or congestion) constrairlts, when compared to the above deterministic coiigestioii rrirdeI not able to estimate shielding and therefore not, &le to minimize shieldirig during routing.

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A system-level solution to domino synthesis with 2 GHz application

Cited by 5 publications

References 10 publications

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Full-chip multilevel routing for power and signal integrity

Probabilistic congestion model considering shielding for crosstalk reduction

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