Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018) 2019
DOI: 10.22323/1.343.0097
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A System-Verilog Verification Environment for the CIC Data Concentrator ASIC of the CMS Outer Tracker Phase-2 Upgrades

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“…The development and simulation of the different ASICs has been carried out using a System-Verilog and Universal Verification Methodology (UVM) multichip framework [6,7], allowing to verify the ASICs' functionality at clock cycle accuracy with single event upset (SEU) injection, and a configurable PU and trigger rate.…”
Section: Front-end Readout Chain For Cms Outer Trackermentioning
confidence: 99%
“…The development and simulation of the different ASICs has been carried out using a System-Verilog and Universal Verification Methodology (UVM) multichip framework [6,7], allowing to verify the ASICs' functionality at clock cycle accuracy with single event upset (SEU) injection, and a configurable PU and trigger rate.…”
Section: Front-end Readout Chain For Cms Outer Trackermentioning
confidence: 99%