A systematic approach for optimized bypass configurations for application-specific embedded processors

Abstract

The diversity of today's mobile applications requires embedded processor cores with a high resource efficiency, that means, the devices should provide a high performance at low area requirements and power consumption. The fine-grained parallelism supported by multiple functional units of VLIW architectures offers a high throughput at reasonable low clock frequencies compared to single-core RISC processors. To efficiently utilize the processor pipeline, common system architectures have to cope with data hazards due to data dependencies between consecutive operations. On the one hand, such hazards can be resolved by complex forwarding circuits (i.e., a pipeline bypass) which forward intermediate results to a subsequent instruction. On the other hand, the pipeline bypass can strongly affect or even dominate the total resource requirements and degrade the maximum clock frequency. In this work the CoreVA VLIW architecture is used for the development and the analysis of application-specific bypass configurations. It is shown that many paths of a comprehensive bypass system are rarely used and may not be required for certain applications. For this reason, several strategies have been implemented to enhance the efficiency of the total system by introducing applicationspecific bypass configurations. The configuration can be carried out statically by only implementing required paths or at runtime by dynamically reconfiguring the hardware. An algorithm is proposed which derives an optimized configuration by iteratively disabling single bypass paths. The adaptation of these applicationspecific bypass configurations allows for a reduction of the critical path by 26%. As a result, the execution time and energy requirements could be reduced by up to 21.5%. Using Dynamic Frequency Scaling (DFS) and dynamic deactivation/reactivation of bypass paths allows for a runtime reconfiguration of the bypass system. This ensures the highest efficiency while processing varying applications. ACM Reference Format:Jungeblut, T., Hübener, B., Porrmann, M., and Rückert, U. 2013. A systematic approach for optimized bypass configurations for application-specific embedded processors.

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture

“…Intermediate results from the last three pipeline stages are forwarded to the RD stage (data bypass) and DC stage (control bypass, condition register only). In [9] we have shown that the number of bypass paths heavily grows with the number of implemented VLIW slots and that many of those paths are rarely used while processing certain applications. Due to this, each single bypass path can be implemented or replaced by a stalling mechanism.…”

“…The width of the instruction memory is set to 128 bit. The EX-DC control bypass is disabled as proposed in our previous work [9]. The processor includes 32 general purpose registers, a trace unit, a bus interface, and a UART unit.…”

“…In previous works, we presented a systematic approach to determine the most efficient bypass-configuration for specific applications [9]. Jungeblut et al [10] present the memory subsystem of the CoreVA processor.…”