A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

Madanayake, H.L.P. Arjuna; Bruton, L.T.

doi:10.1109/tcsi.2008.916612

Cited by 14 publications

(7 citation statements)

References 88 publications

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“…In this work, we use the systolic array architecture for the Gramian matrix computation. A systolic array architecture is produced by the interconnection of a set of attached data processing units (DPU) in a regular way [32], [33]. In parallel, each unit or cell receives data from its upstream neighbors to calculate a part of the result.…”

Section: ) Systolic Array Architecture For Gramian Matrix Computationmentioning

confidence: 99%

Implementation of the RN Method on FPGA using Xilinx System Generator for Nonlinear System Regression

Sayehi¹,

Touali²,

Saidani³

et al. 2017

ijacsa

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Abstract-In this paper, we propose a new approach aiming to ameliorate the performances of the regularization networks (RN) method and speed up its computation time. A considerable rapidity in totaling calculation time and high performance were accomplished through conveying difficult calculation charges to FPGA. Using Xilinx System Generator, a successful HW/SW CoDesign was constructed to accelerate the Gramian matrix computation. Experimental results involving two real data sets of Wiener-Hammerstein benchmark with process noise prove the efficiency of the approach. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 40-50 orders of time, comparing to the CPU simulation.

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Section: ) Systolic Array Architecture For Gramian Matrix Computationmentioning

confidence: 99%

Implementation of the RN Method on FPGA using Xilinx System Generator for Nonlinear System Regression

Sayehi¹,

Touali²,

Saidani³

et al. 2017

ijacsa

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“…The 3-D frequency response is obtained by setting s x = jω x , s y = jω y and s ct = jω ct leading to H( jω x , jω y , jω ct ) = R (R+ j(L x ω x +L y jω y +L ct ω ct ) . 5 Fig. (2b) shows the RF front-end signal processing block connected to each antenna.…”

Section: Review Of 3-d Beam Filteringmentioning

confidence: 99%

“…These systolic arrays compute the recursive 3-D difference equations of the beam filter in one clock cycle, leading to N output samples per clock cycle for an N antenna system. 5 The systolic arrays consist of parallel processing core modules (PPCMs), which are internally optimized using fine-grain pipelining. 5 An antenna array is consist of N x × N y of broadband antenna elements, uniformly placed along x and y axis.…”

Section: Fpga Implementation Of 3-d Filtermentioning

confidence: 99%

“…5 The systolic arrays consist of parallel processing core modules (PPCMs), which are internally optimized using fine-grain pipelining. 5 An antenna array is consist of N x × N y of broadband antenna elements, uniformly placed along x and y axis. Inter-antenna spacing is typically chosen as ∆x = ∆y = λ/2 to satisfy the spatial Nyquist …”

Section: Fpga Implementation Of 3-d Filtermentioning

confidence: 99%

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FPGA architectures for electronically scanned wide-band RF beams using 3-D FIR/IIR digital filters for rectangular array aperture receivers

et al. 2014

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Real-time digital implementation of three-dimensional (3-D) infinite impulse response (IIR) beam filters are discussed. The 3-D IIR filter building blocks have filter coefficients, which are defined using algebraic closed-form expressions that are functions of desired beam personalities, such as the look-direction of the aperture, the bandwidth and sampling frequency of interest, inter antenna spacing, and 3dB beam size. Real-time steering of such 3-D beam filters are obtained by proposed calculation of filter coefficients. Application specific computing units for rapidly calculating the 3-D IIR filter coefficients at nanosecond speed potentially allows fast real-time tracking of low radar cross section (RCS) objects at close range. Proposed design consists of 3-D IIR beam filter with 4 × 4 antenna grid and the filter coefficient generation block in separate FPGAs. The hardware is designed and co-simulated using a Xilinx Virtex-6 XC6VLX240T FPGA. The 3-D filter operates over 90 MHz and filter coefficient computing structure can operate at up to 145 MHz.

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“…In recent work 34–38, it was shown that a systolic‐array architecture 39–60may be optimized for high temporal throughput by using a 2D look‐ahead (LA) 61–65 method, thereby enabling fast beam PW filtering at a real‐time rate of one‐frame‐per‐clock‐cycle (OFPCC), where a frame is theset of time‐synchronous input spatial samples obtained from the ULA. In 37, 38, 66, it was shown that radio‐frequency (RF) antenna signals may be processed at a rate of OFPCC. For example, a speed‐maximized systolic very large‐scale integration (VLSI) array beam filter, implemented using a 1‐GHz application‐specific integrated‐circuit ASIC technology, can achieve a maximum frame‐sampling rate of approximately 1 billion frames per second.…”

Section: Introductionmentioning

confidence: 99%

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

Madanayake

Gunaratne

Bruton

2010

Circuit Theory & Apps

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SUMMARYA systolic architecture has recently been proposed for implementing two-dimensional infinite impulse response (IIR) space-time beam plane-wave filters at a throughput of one-frame-per-clock-cycle for such applications as real-time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M-frames-per-clockcycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look-ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock-cycle limit of the very large-scale integration (VLSI) technology, thereby potentially allowing multi-GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array-based real-time prototype is described, tested and verified for the two-phase case (M = 2) at a technology-limited clock frequency of 50 MHz which corresponds to a throughput of 100 million-frames-per-clock-cycle.

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A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

Cited by 14 publications

References 88 publications

Implementation of the RN Method on FPGA using Xilinx System Generator for Nonlinear System Regression

Implementation of the RN Method on FPGA using Xilinx System Generator for Nonlinear System Regression

FPGA architectures for electronically scanned wide-band RF beams using 3-D FIR/IIR digital filters for rectangular array aperture receivers

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

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