A Technical Guide for the RASP-FIT Tool

Khatri, Abdul Rafay

doi:10.14569/ijacsa.2019.0101279

Cited by 2 publications

(2 citation statements)

References 26 publications

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“…These modified designs are now used for the fault simulation/emulation, digital testing and dependability analysis, with FPGA tools, without much effort. The development of this tool is presented in previous research [11], [12], [15], [13], [16], [17], [18]. In this paper, serial fault simulation is validated for ISCAS'85 benchmark designs.…”

Section: A Rasp-fit Verilog Code Modifiermentioning

confidence: 99%

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Khatri¹,

Hayek²,

Börcsök³

2020

IJACSA

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Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS'85 benchmark design as an example.

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Section: A Rasp-fit Verilog Code Modifiermentioning

confidence: 99%

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Khatri¹,

Hayek²,

Börcsök³

2020

IJACSA

Self Cite

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“…To provide easy usage, a stand-alone app is made using deploytool command of Matlab. This app can be installed on the system having Windows operating system by the user very easily [30]. This tool is developed for the following purposes.…”

Section: Proposed Tmr Code Generatormentioning

confidence: 99%

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

Khatri¹

2020

IJACSA

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The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Faulttolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

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A Technical Guide for the RASP-FIT Tool

Cited by 2 publications

References 26 publications

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

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