A technique to increase the efficiency of high-voltage charge pumps

Hoque, Mohammad Rashedul; Ahmad, Tausif; McNutt, Ty; Mantooth, H. Alan; Mojarradi, Mohammad

doi:10.1109/tcsii.2006.869922

Cited by 36 publications

(18 citation statements)

References 4 publications

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“…Yet, the output voltage level is limited by the breakdown of parasitic p-n junctions between the n+ region and the p-substrate [7]. The silicon-on-insulator (SOI) process [8] and polysilicon diodes [7] overcame such limitations. However, the intrinsic polysilicon layer [7] is not available in standard bulk CMOS processes, and the SOI CMOS process [8] is more expensive.…”

Section: Introductionmentioning

confidence: 99%

“…The silicon-on-insulator (SOI) process [8] and polysilicon diodes [7] overcame such limitations. However, the intrinsic polysilicon layer [7] is not available in standard bulk CMOS processes, and the SOI CMOS process [8] is more expensive. Therefore, developing new circuit techniques in bulk CMOS processes for high voltage generation is of great interest.…”

Section: Introductionmentioning

confidence: 99%

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High voltage charge pump with triple well diodes in a 0.13 µm bulk CMOS process

Sun

Wang

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper presents charge pump circuits with modified triple well diodes as charge transfer switches for charging on-chip pulse generation circuits in a low-voltage bulk CMOS process. Guard-rings and isolation deep n-wells are used to improve the breakdown voltages and reduce leakage currents of the diodes. Model parameters of the triple well diode are extracted based on measured diode characteristics. These parameters are then used to analyze our charge pump. The proposed charge pump circuits are implemented in a commercial 0.13 µm bulk CMOS process. The output voltage of the fourstage charge pump circuit can be up to 18.1 V, which is much higher than the n-well/p-substrate breakdown voltage (~10 V) of the given process.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High voltage charge pump with triple well diodes in a 0.13 µm bulk CMOS process

Sun

Wang

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…For on-chip charge pumps, efficiency in power and area are two major concerns, and both are closely related to charge pump topologies that determine the number of capacitors and switches and losses due to parasitic capacitors. Integrated linear (or Dickson) charge pumps (LQPs) are the most popular implementations due to their simple structure and readily available design procedures [1][2][3][4][5][6][7][8]. With a 2-phase non-overlapping clock, the Fibonacci charge pump (FQP) [9] and the exponential charge pump (EQP) [10,11] promised to achieve very high voltage conversion ratios using fewer capacitors than the LQP, and both are potential candidates for on-chip applications.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications

Lü

et al. 2012

VLSI-SoC: Advanced Research for Systems on Chip

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Charge balance law based on conservation of charge is stated and employed to analyze on-chip linear, Fibonacci and exponential charge pumps. For micro-power on-chip implementations, both the positive-and the negativeplate parasitic capacitors have to be considered. Voltage conversion ratios and efficiencies can be obtained in closed form for single-and dual-branch linear charge pumps, but not for Fibonacci and exponential charge pumps. Instead, a first iteration approximation analysis for computing voltage conversion ratio is proposed. For the linear charge pump, efficiency optimization is achieved by first computing the optimal number of stages, and then obtaining from the required output voltage the reduction factor that is a function of load current, flying capacitor and switching frequency. Using a 0.35μm CMOS process, 8X linear, Fibonacci and exponential charge pumps are designed and their performances are compared and confirmed by extensive Cadence Spectre simulations. It is concluded that linear charge pumps attain the best efficiency.

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“…One of the applications of the active‐diode circuit is Dickson‐type voltage doubler shown in Figure 2 7–13. It consists of two diodes, two capacitors (boosting capacitor, C BST , and output capacitor, C OUT ) and a clock signal.…”

Section: Introductionmentioning

confidence: 99%

“…High power loss occurs at higher values of V A (the upper bound of V SG1 ) since I SD1 is large and is not well-limited. One of the applications of the active-diode circuit is Dickson-type voltage doubler shown in Figure 2 [7][8][9][10][11][12][13]. It consists of two diodes, two capacitors (boosting capacitor, C BST , and output capacitor, C OUT ) and a clock signal.…”

Section: Introductionmentioning

confidence: 99%

Improved active‐diode circuit used in voltage doubler

Jia

Leung

2012

Circuit Theory & Apps

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SUMMARYAn improved active-diode circuit, which makes use of positive feedback to achieve fast on/off transition, is presented in this paper. The proposed active-diode circuit can be embedded into a voltage doubler to replace the commonly used dead-time circuit and to eliminate reverse current. In addition, the relationship between oscillation frequency, boosting and output capacitances, load-and on-resistances of the power switch and the output voltage is analysed, to investigate a methodology to retain high voltage gain of a voltage doubler. The proposed active-diode circuit is applied to a voltage doubler implemented in a commercial 0.35-m process with threshold voltage of about 0.68 V. The input voltage, maximum output current and oscillation frequency of the voltage doubler are 1 V, 1 mA and 0.4 MHz, respectively. Moreover, the used boosting and output capacitances are 22 nF. The highest power efficiency achieved is 83% at a load current of 0.47 mA.

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A technique to increase the efficiency of high-voltage charge pumps

Cited by 36 publications

References 4 publications

High voltage charge pump with triple well diodes in a 0.13 µm bulk CMOS process

High voltage charge pump with triple well diodes in a 0.13 µm bulk CMOS process

Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications

Improved active‐diode circuit used in voltage doubler

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A technique to increase the efficiency of high-voltage charge pumps

Cited by 36 publications

References 4 publications

High voltage charge pump with triple well diodes in a 0.13 &#x00B5;m bulk CMOS process

High voltage charge pump with triple well diodes in a 0.13 &#x00B5;m bulk CMOS process

Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications

Improved active‐diode circuit used in voltage doubler

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Product

Resources

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High voltage charge pump with triple well diodes in a 0.13 µm bulk CMOS process

High voltage charge pump with triple well diodes in a 0.13 µm bulk CMOS process