A Temperature-Aware Framework on gm
 /ID
 -Based Methodology Using 180 nm SOI From −40 °C to 200 °C

Martins, João R. Raposo de O.; Mostafa, Ali; Jerome, J. Terrence Jose; Hamani, Rachid; Alvès, Francisco; Ferreira, Pietro Maris

doi:10.1109/ojcas.2021.3067377

Cited by 8 publications

(4 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is important to know the current of M 2 , which will vary depending on the current of M 5 if current scaling is desired. in this case, M 5 should be sized first according to (14). gm 5/gm 1 allows for greater control over the noise contribution of this device, however, it should be less than 1 to prevent noise amplification.…”

Section: B M 5 Sizingmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

Tarkhan

2022

IEEE Access

View full text Add to dashboard Cite

The input-referred noise (IRN) is one of the most crucial performance indicators for analog front-ends (AFEs) of neural recording devices. We present in this paper, a novel design approach for a low-noise amplifier (LNA) based on the transistor optimization method in CMOS technology. Because flicker noise is predominant in neural recording applications, the AFE has been designed so as to meet input-referred flicker noise specifications, whereas thermal noise contributions are monitored and controlled by flicker noise corner frequencies. Transistor optimization is accomplished by using a lookup table that encapsulates its performance based on its current density. Initially, transistors are optimized based on flicker noise performance; later, they may be further optimized based on their size, power consumption, transconductance, or thermal noise contribution. The proposed approach has been validated by designing a folded-cascode amplifier with an IRN ranging from 2 to 8 µV rms . The results of the simulation show that the errors of our design methodology are less than 10%, which is less than those of gm /I D and the inversion coefficient methods. The proposed LNA achieves 2.1 µV rms while consuming 0.83 µW from 1.2 V supply.

show abstract

Section: B M 5 Sizingmentioning

confidence: 99%

“…Consequently, other methods such as gm /I D and inversion coefficient have been proposed. The gm /I D is a method based on transconductance efficiency for estimating the device size [14]- [16]. But this method can be useful in sizing transistors in the moderate inversion region.…”

Section: Introductionmentioning

confidence: 99%

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

Tarkhan

2022

IEEE Access

View full text Add to dashboard Cite

show abstract

“…In [19], electrical characterization of 180-nm and 500-nm SOI CMOS devices up to 300°C shows good performance and the existing SPICE model BSIMSOI has been adapted to cover the extended temperature range. The work in [20] instead is more oriented to the design techniques for high temperature circuits, based on 𝑔 𝑚 /𝐼 𝑑 methodology for Zero Temperature Coefficient (ZTC) biasing. The following work [21] by the same group extends the proposed design methodology up to an operation temperature of 250°C, assessing the functionality with chip measurements on a Voltage Controlled Oscillator.…”

Section: Introductionmentioning

confidence: 99%

“…Compared with previous works, we introduce a novel approach focused on devices available in the PDK of a standard SOI process to implement temperature-resilient design techniques at the circuit level. The proposed techniques can be used together with ZTC biasing strategies, as the one proposed in [20], to effectively improve the robustness of ICs in extreme temperature environments.…”

Section: Introductionmentioning

confidence: 99%

Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C

Sbrana,

Catania,

Paliy

et al. 2024

IEEE Access

View full text Add to dashboard Cite

In this paper, we discuss the challenges at the device and circuit level that must be addressed to design reliable silicon CMOS integrated circuits operating in high-temperature environments. We present experimental results on representative devices fabricated with a 180 nm CMOS SOI platform, which have been characterized up to 300°C, discuss issues arising at high temperature, and propose possible solutions. A BJT-based temperature sensor core is also described and evaluated across the same extended temperature range. We also propose and discuss design criteria optimized for a wide range of operating temperature. A sufficient on/off current ratio can be achieved by taking advantage of the isolation provided by low-leakage CMOS SOI process, while operation at low current density must be ensured to mitigate electromigration effects. Within these conditions, low-power precise sensing circuits can be effectively implemented with operating temperature up to 300°C, that are extremely relevant for industrial, mobility, and space applications.INDEX TERMS High temperature electronics; harsh environment electronics; CMOS SOI.

show abstract

Characterization of Multi-$$V_t$$ Transistors for Analog IC Design in Sub-nanometer Technologies

Banerjee,

Rani,

Santosh

et al. 2024

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

A Temperature-Aware Framework on g_m /I_D -Based Methodology Using 180 nm SOI From −40 °C to 200 °C

Cited by 8 publications

References 28 publications

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C

Characterization of Multi-$$V_t$$ Transistors for Analog IC Design in Sub-nanometer Technologies

Contact Info

Product

Resources

About

A Temperature-Aware Framework on gm /ID -Based Methodology Using 180 nm SOI From −40 °C to 200 °C

Cited by 8 publications

References 28 publications

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

A Novel Current Density Based Design Approach of Low-Noise Amplifiers

Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C

Characterization of Multi-$$V_t$$ Transistors for Analog IC Design in Sub-nanometer Technologies

Contact Info

Product

Resources

About

A Temperature-Aware Framework on g_m /I_D -Based Methodology Using 180 nm SOI From −40 °C to 200 °C