A Temperature-Compensated 57 PPM/°C 10MHz, 2.4μW Stacked Ring Oscillator

Abstract

Ring oscillators are one of the simplest, smallest and most energy-efficient topologies when it comes to clock generation. Being implemented using a chain of digital inverters, their oscillation frequency can be set by the inverters count in the chain and the delay of each inverter. This is an advantage when considering the simplicity and size, however, it is also the cause for high frequency variation with temperature. In this paper we propose an ultra-low power oscillator circuit that exploits a stack of small ring oscillators for supply current reuse and injection locking, which provides phase noise improvement. Frequency stability is achieved through a feedback loop that relies on a frequency-to-voltage converter with improved linearity and reduced temperature sensitivity based on MOS capacitors. Simulation results show that the oscillation frequency changes ±0.4% from 0 to 70ºC (57 ppm/ • C) while consuming 2.4 µW at 10 MHz, with a phase noise of -88.9 dBc/Hz at 100 kHz offset.Index Terms-Frequency to voltage converter, MOSCAPs, ring oscillator, stacked oscillator.

Ultra Low Power Temperature Compensated Complementary Metal Oxide Semiconductor Ring Oscillator in Subthreshold

“…The operational amplifier puts the voltageVSD1 across a resistor with low TC to provide required ICTAT that is given by Equation (12).…”

“…So, in order to achieve desirable frequency stability, using compensation techniques [4,5] is mandatory. Thus, several researches have been devoted to effective compensation of the CMOS oscillators [4,[6][7][8][9][10][11][12][13]. Considering the type of application that oscillator is designed for, the appropriate compensation technique is developed.…”

“…Using a frequency to voltage (FV) converter in a feedback loop the TC of a current-reused stacked ring oscillator has been improved by Rodrigues et al [12]; however, the circuit suffers from the high complexity and nonlinearity of the FV. In order to reduce the TC nonlinearity of an RC oscillator in a wiredcommunication system a frequency locked loop (FLL) is used by Park et al [13] that locks the period of the oscillator to a reference time constant.…”

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

“…Inverting stage produces 180 0 phase shift, to make 360 0 phase shifts from output to input, a phase lead or phase lag network should be placed in the feedback path. The choosing of resistor value is based on the condition that the input impedance of a network must be large in comparison to the output impedance of the inverter amplifier stage[19][20][21].…”