A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators

Ayupov, Andrey; Yesil, Serif; Özdal, Mustafa; Burns, Steven; Öztürk, Özcan

doi:10.1109/tcad.2017.2706562

Cited by 14 publications

(5 citation statements)

References 27 publications

(26 reference statements)

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“…2017 TuNao [30] ASIC COO Y V/Async Various F Cusha [7] 3 2017 GAA [83] ASIC CSR Y V/Async Various P Host 4 2018 Ozdal et al [31] ASIC CSR Y V/Async Various P GAP [116] 5…”

Section: Summary Of Resultsmentioning

confidence: 99%

“…Source-Oriented [15,27,69,[77][78][79][80] Destination-Oriented [16,26,30,73,81] Grid [28,70,82] Heuristic [29,31,32,75,76,83,84] Source-oriented Partition. it is convenient to determine the partitions that need the updated vertex property in the graph processing.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…For instance, FPGAs have been used in Microsoft datacenter for energy efficiency improvement [23] . Specifically in terms of graph processing, it has been also witnessed that a large number of relevant studies build their graph processing accelerators based on FPGA [24][25][26][27][28] and ASIC [16,[29][30][31] . Evaluation on these http://www.riscv.org, Jan. 2019.…”

Section: Introductionmentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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“…2017 TuNao [30] ASIC COO Y V/Async Various F Cusha [7] 3 2017 GAA [83] ASIC CSR Y V/Async Various P Host 4 2018 Ozdal et al [31] ASIC CSR Y V/Async Various P GAP [116] 5…”

Section: Summary Of Resultsmentioning

confidence: 99%

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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“…Data between the compute leaves is communicated over a network on chip. In [8], a design methodology based on the BSP model is proposed. Common architectural features are represented as templates which are specified with user-defined functions for GAS.…”

Section: Compressed Sparse Row (Csr)mentioning

confidence: 99%

Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges

Dann¹,

Ritter²,

Fröning³

2020

Preprint

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Non-relational database systems (NRDS), such as graph, document, key-value, and wide-column, have gained much attention in various trending (business) application domains like smart logistics, social network analysis, and medical applications, due to their data model variety and scalability. The broad data variety and sheer size of datasets pose unique challenges for the system design and runtime (incl. power consumption). While CPU performance scaling becomes increasingly more difficult, we argue that NRDS can benefit from adding field programmable gate arrays (FPGAs) as accelerators. However, FPGA-accelerated NRDS have not been systematically studied, yet.To facilitate understanding of this emerging domain, we explore the fit of FPGA acceleration for NRDS with a focus on data model variety. We define the term NRDS class as a group of non-relational database systems supporting the same data model. This survey describes and categorizes the inherent differences and nontrivial trade-offs of relevant NRDS classes as well as their commonalities in the context of common design decisions when building such a system with FPGAs. For example, we found in the literature that for keyvalue stores the FPGA should be placed into the system as a smart network interface card (SmartNIC) to benefit from direct access of the FPGA to the network. However, more complex data models and processing of other classes (e. g., graph and document) commonly require more elaborate near-data or socket accelerator placements where the FPGA respectively has the only

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“…It is often only in embedded systems with highperformance needs and very limited power restrictions that the industry turn to ASICs. Despite this, there are still ASIC graph accelerators presented [3,6,25,43,62]. Each, despite their narrow scope, offer incredible speedups and power savings for the process that they are specifically designed for.…”

Section: Agp Syntaxmentioning

confidence: 99%

A Message Passing Many-Core Architecture for an Asynchronous Graph Programming Model

Cook¹

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Noticeable improvements in processor performance have been achieved by researching programming models, control flow parallelization, general architecture, memory access, and code compilation [53][4]. In this thesis, we seek to improve general processing by applying a many-core message passing (MPMC) architecture with a novel Asynchronous Graph Programming model (AGP).AGP abstracts higher-level languages into a graph of single instructions providing very high levels of parallelism and asynchronicity. The MPMC architecture utilizes a novel method of segmenting a graph among cores in tandem with the many-core model to exploit AGPs parallelism.We evaluate the MPMC architecture implementing a functional simulation that, although incapable of providing empirical measurements, provides an efficient method of evaluation that helps accelerate the development cycle. We found that the MPMC architecture can reach a 97% improvement in execution time from a single-core configuration, with room to improve given more cores and better node allocation strategies.

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A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators

Cited by 14 publications

References 27 publications

A Survey on Graph Processing Accelerators: Challenges and Opportunities

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges

A Message Passing Many-Core Architecture for an Asynchronous Graph Programming Model

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